SNVU695A June 2020 – January 2022 LP87702-Q1
Table 2-1 provides the recommended supply voltage range specifications for different AWR1843 supply rails. The external supply voltage on this pin should be 1.3 V in case the application uses an internal LDO on a 1.0 V or 1.3 V RF rail. If an internal LDO is not used or bypassed, then an external supply voltage on this pin should be 1.0 V. Often an internal LDO is not used as it increases the AWR internal power dissipation. A special power supply sequencing is not needed, but all the input supply rails should be settled before releasing the reset/power good signal to the AWR device. The CAN PHY may need to be controlled by both the PMIC and AWR to avoid a glitch in case the AWR IO enables the CAN PHY when the 3.3 V AWR rail is ramping but the 1.8 V rail is not active.
| Input | Description | Minimum (V) | Nominal (V) | Maximum (V) |
|---|---|---|---|---|
| VDDIN | 1.2 V digital power supply | 1.14 | 1.2 | 1.32 |
| VIN_SRAM | 1.2 V power rail for internal SRAM | 1.14 | 1.2 | 1.32 |
| VNWA | 1.2 V power rail for SRAM array back bias | 1.14 | 1.2 | 1.32 |
| VIOIN | I/O supply (3.3 V of 1.8 V). All CMOS I/Os would operate on this supply. | 3.15 | 3.3 | 3.45 |
| 1.71 | 1.8 | 1.89 | ||
| VIOIN_18 | 1.8 V supply for CMOS I/O | 1.71 | 1.8 | 1.9 |
| VIN_18CLK | 1.8 V supply for clock module | 1.71 | 1.8 | 1.9 |
| VIOIN_18IFF | 1.8 V supply for LVDS port | 1.71 | 1.8 | 1.9 |
| VIN_13RF1 | 1.3 V analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board. | 1.23 | 1.3 | 1.36 |
| VIN_13RF2 | ||||
| VIN_13RF1 (1 V Internal LDO bypass mode) | 0.95 | 1.0 | 1.05 | |
| VIN_13RF2 (1 V Internal LDO bypass mode) | ||||
| VIN18BB | 1.8 V analog baseband power supply | 1.71 | 1.8 | 1.9 |
| VIN_18VCO | 1.8 V RF VCO supply | 1.71 | 1.8 | 1.9 |