SNVU926 October   2024 LP5810

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction/Feature Overview
    1. 1.1 Overview
  4. 2 Register Maps
    1. 2.1  Register Map Table
    2. 2.2  Device_Enable Registers
    3. 2.3  Config Registers
    4. 2.4  Command Registers
    5. 2.5  LED_Enable Registers
    6. 2.6  Fault_Clear Registers
    7. 2.7  Reset Registers
    8. 2.8  Manual_DC Registers
    9. 2.9  Manual_PWM Registers
    10. 2.10 Autonomous_DC Registers
    11. 2.11 LED_0_Autonomous_Animation Registers
    12. 2.12 LED_1_Autonomous_Animation Registers
    13. 2.13 LED_2_Autonomous_Animation Registers
    14. 2.14 LED_3_Autonomous_Animation Registers
    15. 2.15 Flag Registers
  5.   Revision History

2.10 Autonomous_DC Registers

Table 2-48 lists the memory-mapped registers for the Autonomous_DC registers. All register offset addresses not listed in Table 2-48 should be considered as reserved locations and the register contents should not be modified.

Table 2-48 AUTONOMOUS_DC Registers
OffsetAcronymRegister NameSection
50hAuto_DC_0LED_0 current setting in autonomous modeGo
51hAuto_DC_1LED_1 current setting in autonomous modeGo
52hAuto_DC_2LED_2 current setting in autonomous modeGo
53hAuto_DC_3LED_3 current setting in autonomous modeGo

Complex bit access types are encoded to fit into small table cells. Table 2-49 shows the codes that are used for access types in this section.

Table 2-49 Autonomous_DC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

2.10.1 Auto_DC_0 Register (Offset = 50h) [Reset = 00h]

Auto_DC_0 is shown in Figure 2-31 and described in Table 2-50.

Return to the Summary Table.

Figure 2-31 Auto_DC_0 Register
76543210
auto_dc_0
R/W-0h
Table 2-50 Auto_DC_0 Register Field Descriptions
BitFieldTypeResetDescription
7-0auto_dc_0R/W0h LED_0 current setting in autonomous mode; 0h = 0; 1h = 0.39%; 2h = 0.78%; ...
80h = 50.2%; ...
FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.10.2 Auto_DC_1 Register (Offset = 51h) [Reset = 00h]

Auto_DC_1 is shown in Figure 2-32 and described in Table 2-51.

Return to the Summary Table.

Figure 2-32 Auto_DC_1 Register
76543210
auto_dc_1
R/W-0h
Table 2-51 Auto_DC_1 Register Field Descriptions
BitFieldTypeResetDescription
7-0auto_dc_1R/W0h LED_1 current setting in autonomous mode;; 0h = 0; 1h = 0.39%; 2h = 0.78%; ...
80h = 50.2%; ...
FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.10.3 Auto_DC_2 Register (Offset = 52h) [Reset = 00h]

Auto_DC_2 is shown in Figure 2-33 and described in Table 2-52.

Return to the Summary Table.

Figure 2-33 Auto_DC_2 Register
76543210
auto_dc_2
R/W-0h
Table 2-52 Auto_DC_2 Register Field Descriptions
BitFieldTypeResetDescription
7-0auto_dc_2R/W0h LED_2 current setting in autonomous mode; 0h = 0; 1h = 0.39%; 2h = 0.78%; ...
80h = 50.2%; ...
FDh = 99.2%; FEh = 99.6%; FFh = 100%

2.10.4 Auto_DC_3 Register (Offset = 53h) [Reset = 00h]

Auto_DC_3 is shown in Figure 2-34 and described in Table 2-53.

Return to the Summary Table.

Figure 2-34 Auto_DC_3 Register
76543210
auto_dc_3
R/W-0h
Table 2-53 Auto_DC_3 Register Field Descriptions
BitFieldTypeResetDescription
7-0auto_dc_3R/W0h LED_3 current setting in autonomous mode; 0h = 0; 1h = 0.39%; 2h = 0.78%; ...
80h = 50.2%; ...
FDh = 99.2%; FEh = 99.6%; FFh = 100%