SNVU926 October 2024 LP5810
Table 2-27 lists the memory-mapped registers for the LED_Enable registers. All register offset addresses not listed in Table 2-27 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 20h | LED_EN_1 | Enable the LEDs of LED_0 to LED_3 | Go |
Complex bit access types are encoded to fit into small table cells. Table 2-28 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
LED_EN_1 is shown in Figure 2-20 and described in Table 2-29.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | led_en_3 | led_en_2 | led_en_1 | led_en_0 | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0h | Reserved |
| 3 | led_en_3 | R/W | 0h | LED_3 Enable; 0h = Disabled; 1h = Enabled |
| 2 | led_en_2 | R/W | 0h | LED_2 Enable; 0h = Disabled; 1h = Enabled |
| 1 | led_en_1 | R/W | 0h | LED_1 Enable; 0h = Disabled; 1h = Enabled |
| 0 | led_en_0 | R/W | 0h | LED_0 Enable; 0h = Disabled; 1h = Enabled |