SPNA241 August   2019 RM41L232 , RM42L432 , RM44L520 , RM44L920 , RM46L430 , RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS0714 , TMS570LS0714-S , TMS570LS0914 , TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS20206 , TMS570LS20206-EP , TMS570LS20216 , TMS570LS20216-EP , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS3134 , TMS570LS3135 , TMS570LS3137 , TMS570LS3137-EP

 

  1.   CAN Bus Bootloader for Hercules Microcontrollers
    1.     Trademarks
    2. 1  Introduction
    3. 2  Hardware Requirements
    4. 3  CAN Settings
    5. 4  Software Coding and Compilation
    6. 5  Exception Vector Table
    7. 6  ECC Generation for Bootloader Code
    8. 7  ECC Generation for Application Code
    9. 8  During Bootloader Execution
    10. 9  Bootloader Flow
    11. 10 CAN Bootloader Operation
    12. 11 CAN Bootloader Protocol
    13. 12 Create Application for Use With the Bootloader
    14. 13 Sample Code for PC-Side Application
    15. 14 References

8 During Bootloader Execution

During bootloader execution:

  • MCU operates in supervisor mode: The F021 Flash APIs are called in bootloader to erase flash sectors and program the application code. On the ARM Cortex-R4/R5 devices, the flash APIs must be run in a privilege mode (a mode other than user) to allow access to the Flash memory controller registers.
  • MCU Clock is reconfigured and is maintained throughout the bootloader execution. The flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash can support a maximum CPU clock speed in pipelined mode with appropriate address wait state and data wait states. Please make sure the RWAIT is set properly for the specified system frequency.
    • Clock Source: OSCIN = 16 MHz
    • System clock (HCLK): 150 MHz for TMS570LCx and RM57x devices, 160 MHz for TMS570LS31x/12x and RM48/RM46 devices, 100 MHz for TMS570LS07x and RM44 devices, 80 MHz for TMS570LS04x and RM42 devices.
    • Peripheral clock (VCLK): 75 MHz for TMS570LCx and RM57x devices, 90 MHz for TMS570LS31x/12x and RM48/RM46 devices, 100 MHz for TMS570LS07x and RM44 devices, 80 MHz for TMS570LS04x and RM42 devices.
  • The interrupt is disabled in bootloader example code. If the interrupt is used in bootloader, it has to be disabled before the code is branched to the application code.
  • CAN bit timing: The interrupt is disabled in bootloader example code. If the interrupt is used in bootloader, it has to be disabled before the code is branched to the application code. The default setting is 500 kbps. You can modify the baudrate through HALCoGen.
  • F021 Flash API Version 2.01.01 is used. The flash API and its related code must be executed from SRAM.

The user application must be in raw binary format. The hex format is not supported.