16/32 Bit RISC Flash MCU, Arm Cortex-R4F

TMS570LS3134

ACTIVE

Product details

CPU Arm Cortex-R4F Frequency (MHz) 160, 180 ADC 2 x 12-Bit (24ch) GPIO 64, 144 UART 2 Number of I2Cs 1 Features Hercules high-performance microcontroller TI functional safety category Functional Safety-Compliant Operating temperature range (C) -40 to 125
CPU Arm Cortex-R4F Frequency (MHz) 160, 180 ADC 2 x 12-Bit (24ch) GPIO 64, 144 UART 2 Number of I2Cs 1 Features Hercules high-performance microcontroller TI functional safety category Functional Safety-Compliant Operating temperature range (C) -40 to 125
LQFP (PGE) 144 484 mm² 22 x 22 NFBGA (ZWT) 337 256 mm² 16 x 16
  • High-Performance Microcontroller for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single- and Double-Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • System Clock up to 180 MHz
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
  • Integrated Memory
    • 3MB of Program Flash With ECC (LS3134)
    • 2MB of Program Flash With ECC (LS2134/2124)
    • 256KB of RAM With ECC (LS3134/2134)
    • 192KB of RAM With ECC (LS2124)
    • 64KB of Flash With ECC for Emulated EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt (RTI) Timer OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • Separate Nonmodulating PLL
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each With Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Standard Serial Communication Interface (SCI)
    • Local Interconnect Network (LIN) Interface Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
    • Two Standard Serial Peripheral Interfaces (SPIs)
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM Each With Parity Protection
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Transfer Unit (HTU) With MPU for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared With ADC1
    • 64 Result Buffers With Parity Protection Each
  • General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
    • 16 Pins on the ZWT Package
    • 10 Pins on the PGE Package
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • JTAG Security Module
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 337-Ball Grid Array (ZWT) [Green]

All trademarks are the property of their respective owners.

  • High-Performance Microcontroller for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single- and Double-Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • System Clock up to 180 MHz
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
  • Integrated Memory
    • 3MB of Program Flash With ECC (LS3134)
    • 2MB of Program Flash With ECC (LS2134/2124)
    • 256KB of RAM With ECC (LS3134/2134)
    • 192KB of RAM With ECC (LS2124)
    • 64KB of Flash With ECC for Emulated EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt (RTI) Timer OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • Separate Nonmodulating PLL
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each With Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Standard Serial Communication Interface (SCI)
    • Local Interconnect Network (LIN) Interface Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
    • Two Standard Serial Peripheral Interfaces (SPIs)
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM Each With Parity Protection
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Transfer Unit (HTU) With MPU for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared With ADC1
    • 64 Result Buffers With Parity Protection Each
  • General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
    • 16 Pins on the ZWT Package
    • 10 Pins on the PGE Package
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • JTAG Security Module
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 337-Ball Grid Array (ZWT) [Green]

All trademarks are the property of their respective owners.

The TMS570LS31x4/21x4 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The TMS570LS31x4/21x4 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3134 device has 3MB of integrated flash and 256KB of data RAM. The TMS570LS2134 device has 2MB of integrated flash and 256KB of data RAM. The TMS570LS2124 device has 2MB of integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.

The TMS570LS31x4/21x4 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, and one I2C module. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals, or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS31x4/21x4 device is an ideal solution for high-performance real-time control applications with safety-critical

The TMS570LS31x4/21x4 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The TMS570LS31x4/21x4 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3134 device has 3MB of integrated flash and 256KB of data RAM. The TMS570LS2134 device has 2MB of integrated flash and 256KB of data RAM. The TMS570LS2124 device has 2MB of integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.

The TMS570LS31x4/21x4 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, and one I2C module. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 peripheral requests, and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals, or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS31x4/21x4 device is an ideal solution for high-performance real-time control applications with safety-critical

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More information

Hercules TMS570LS3134 is certified by TÜV SÜD to be capable of achieving IEC 61508 SIL 3 helping to make it easier to develop functional safety applications. Download certificate now.

Technical documentation

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Type Title Date
* Data sheet TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller datasheet (Rev. B) 19 May 2015
* Errata TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision C) (Rev. G) 31 May 2016
* Errata TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision D) (Rev. B) 31 May 2016
* User guide TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (Rev. C) 01 Mar 2018
Technical article 5 ways high-performance MCUs are reshaping the industry 12 Jul 2021
More literature Hercules™ Diagnostic Library Test Automation Unit User Guide (Rev. B) 09 Jan 2020
More literature HALCoGen-CSP 04.07.01 (Rev. C) 08 Jan 2020
User guide HALCoGen-CSP Installation Guide (Rev. B) 08 Jan 2020
User guide HALCoGen-CSP User's Guide (Rev. C) 08 Jan 2020
User guide Hercules Diagnostic Library -TAU Installation Guide (Rev. B) 08 Jan 2020
User guide Hercules Diagnostic Library CSP Without LDRA 29 Oct 2019
More literature Diagnostic Library CSP Release Notes 17 Oct 2019
More literature SafeTI™ Hercules™ Diagnostic Library Release Notes (Rev. A) 24 Sep 2019
Application note HALCoGen Ethernet Driver With lwIP Integration Demo and Active Webserver Demo 13 Sep 2019
Application note Hercules PLL Advisory SSWF021#45 Workaround (Rev. B) 09 Sep 2019
Application note CAN Bus Bootloader for Hercules Microcontrollers 21 Aug 2019
Application note HALCoGen CSP Without LDRA Release_Notes 19 Aug 2019
User guide HALCoGen-CSP Without LDRA Installation Guide 19 Aug 2019
User guide HALCoGen-CSP Without LDRA User's Guide 19 Aug 2019
User guide Hercules Diagnostic Library - Without LDRA Installation Guide 19 Aug 2019
User guide Hercules™ Diag Lib Test Automation Unit Without LDRA User's Guide 19 Aug 2019
Functional safety information Certification for SafeTI Functional Safety Hardware Process (Rev. A) 07 Jun 2019
Application note Interfacing the Embedded 12-Bit ADC in a TMS570LS31x/21x and RM4x Series MCUs (Rev. A) 20 Apr 2018
Application note FreeRTOS on Hercules Devices_new 19 Apr 2018
Application note Sharing FEE Blocks Between the Bootloader and the Application 07 Nov 2017
Application note Sharing Exception Vectors on Hercules™ Based Microcontrollers 27 Mar 2017
Application note Hercules AJSM Unlock (Rev. A) 19 Oct 2016
Application note How to Create a HALCoGen Based Project For CCS (Rev. B) 09 Aug 2016
Application note Using the CRC Module on Hercules™-Based Microcontrollers 04 Aug 2016
More literature Functional Safety Audit: SafeTI Functional Safety Hardware Development (Rev. A) 25 Apr 2016
Application note High Speed Serial Bus Using the MibSPIP Module on Hercules-Based MCUs 22 Apr 2016
Certificate TUEV SUED Certification for TMS570LS31x and TMS570LS21x (Rev. B) 18 Feb 2016
Functional safety information Safety Manual for TMS570LS31x/21x Hercules ARM-Based Safety Critical MCUs (Rev. D) 18 Feb 2016
Application note Enabling Functional Safety Using SafeTI Diagnostic Library 18 Dec 2015
White paper Hercules™ MCU: Features Applicable to Use in High-Speed Rail 02 Nov 2015
Application note Triggering ADC Using Internal Timer Events on Hercules MCUs 19 Oct 2015
White paper Extending TI’s Hercules MCUs with the integrated flexible HET 29 Sep 2015
Application note Continuous Monitor of the PLL Frequency With the DCC 24 Jul 2015
Application note PWM Generation and Input Capture Using HALCoGen N2HET Module 30 Jun 2015
White paper Foundational Software for Functional Safety 12 May 2015
Application note Sine Wave Generation Using PWM With Hercules N2HET and HTU 12 May 2015
Application note Triangle/Trapezoid Wave Generation Using PWM With Hercules N2HET 01 May 2015
Application note Nested Interrupts on Hercules ARM Cortex-R4/5-Based Microncontrollers 23 Apr 2015
White paper Latch-Up White Paper 22 Apr 2015
Application note Interrupt and Exception Handling on Hercules ARM Cortex-R4/5-Based MCUs 20 Apr 2015
Application note Monitoring PWM Using N2HET 02 Apr 2015
Application note Hercules SCI With DMA 22 Mar 2015
Certificate TÜV NORD Certificate for Functional Safety Software Development Process 03 Feb 2015
Application note Calculating Equivalent Power-on-Hours for Hercules Safety MCUs 26 Jan 2015
Application note Limiting Clamp Currents on TMS470/TMS570 Digital and Analog Inputs (Rev. A) 08 Dec 2014
Application note Comp Cons: Mig from 570LS31x/21x or 570LS12x/11x to 570LS04/03x Safety MCUs (Rev. A) 22 Sep 2014
User guide TUV SUD ISO-13849 Safety Architecture Concept Study 02 Jul 2014
More literature HaLCoGen Release Notes 25 Jun 2014
Application note Compatibility Considerations: Migrating TMS570LS31x/21x to TMS570LS12x/11x (Rev. A) 19 Feb 2014
Application note Interfacing TPS65381 With Hercules Microcontrollers (Rev. A) 14 Feb 2014
User guide Trace Analyzer User's Guide (Rev. B) 18 Nov 2013
White paper IEC 60730 and UL 1998 Safety Standard Compliance Made Easier with TI Hercules 03 Oct 2013
Application note CAN Bus Bootloader for TMS570LS31X MCU 16 Sep 2013
Application note SPI Bootloader for Hercules TMS570LS31X MCU 16 Sep 2013
Application note UART Bootloader for Hercules TMS570LS31X MCU 16 Sep 2013
White paper Model-Based Tool Qualification of the TI C/C++ ARM® Compiler 06 Jun 2013
Application note Initialization of Hercules ARM Cortex-R4F Microcontrollers (Rev. D) 29 May 2013
White paper Accelerating safety-certified motor control designs (Rev. A) 04 Oct 2012
Application note Reduction of Power Consumption for TMS570LS3137 17 Sep 2012
Application note Hercules Family Frequency Slewing to Reduce Voltage and Current Transients 05 Jul 2012
Application note Basic PBIST Configuration and Influence on Current Consumption (Rev. C) 12 Apr 2012
Application note Verification of Data Integrity Using CRC 17 Feb 2012
Application note FlexRay Transfer Unit (FTU) Setup 26 Jan 2012
Application note Important ARM Ltd Application Notes for TI Hercules ARM Safety MCUs 17 Nov 2011
Application note Execution Time Measurement for Hercules ARM Safety MCUs (Rev. A) 04 Nov 2011
Application note Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x (Rev. A) 20 Oct 2011
Application note Use of All 1'’s and All 0's Valid in Flash EEPROM Emulation 27 Sep 2011
Application note 3.3 V I/O Considerations for Hercules Safety MCUs (Rev. A) 06 Sep 2011
Application note ADC Source Impedance for Hercules ARM Safety MCUs (Rev. B) 06 Sep 2011
Application note Configuring a CAN Node on Hercules ARM Safety MCUs 06 Sep 2011
Application note Configuring the Hercules ARM Safety MCU SCI/LIN Module for UART Communication (Rev. A) 06 Sep 2011
Application note Leveraging the High-End Timer Transfer Unit on Hercules ARM Safety MCUs (Rev. A) 06 Sep 2011
White paper Hercules™ Microcontrollers: Real-time MCUs for safety-critical products 02 Sep 2011
Application note ECC Handling in TMSx70-Based Microcontrollers 23 Feb 2011
User guide TI ICEPick Module Type C Reference Guide Public Version 17 Feb 2011
Application note NHET Getting Started (Rev. B) 30 Aug 2010
Application note Generating Operating System Tick Using RTI on a Hercules ARM Safety MCU 13 Jul 2010
Application note Usage of MPU Subregions on TI Hercules ARM Safety MCUs 10 Mar 2010
User guide TI Assembly Language Tools Enhanced High-End Timer (NHET) Assembler User's Guide 04 Mar 2010
White paper Discriminating between Soft Errors and Hard Errors in RAM White Paper 04 Jun 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

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Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Development kit

TMDS570LS31HDK — Hercules TMS570LS31x/21x Development Kit

The TMS570LS31 Hercules™ Development Kit is based on the IEC 61508 SIL 3 and ISO 26262 ASIL D certified TMS570LS3137 and is ideal for getting started on development with TMS570LS31x/21x series of the Hercules TMS570 microcontroller family. The development board features RJ45 10/100 Ethernet, two (...)

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Code example or demo

HERCULES_SAFETY_MCU_DEMOS — Hercules Safety MCU Demos

The Hercules Safety MCU Demos are designed to highlight key safety, data acquisition and control features of the Hercules platform of microcontrollers. The demos are designed to be run on a PC in conjunction with either a Hercules USB Development Sick or a Hercules Development Kit (HDK).
Driver or library

HERCULES-DSPLIB — Hercules™ Safety MCU Cortex™-R4 CMSIS DSP Library

TI's Cortex-R4 DSP library conforms to ARM’s Cortex Microcontroller Software Interface Standard (CMSIS), a standardized hardware abstraction layer for the Cortex processor series. The CMSIS-DSP library includes 60+ functions covering vector operations, matrix computing, complex arithmetic, filter (...)
Driver or library

HERCULES-F021FLASHAPI — HERCULES F021FLASHAPI

The F021 Flash Application Programming Interface (API) provides a software library of functions to program, erase, and verify F021 on-chip Flash memory. These functions must be used when creating Flash bootloaders or other programming utilities for F021 Flash based microcontrollers. The Hercules (...)
Driver or library

SAFETI_DIAG_LIB — SafeTI Hercules Diagnostic Library

The Hercules SafeTI™ Diagnostic Library is a collection of software functions and response handlers for various safety features of the Hercules Safety MCUs. The Hercules SafeTI Diagnostic Library runs in the context of the caller's protection environment and all responses are handled in the (...)
IDE, configuration, compiler or debugger

CCSTUDIO-SAFETY — Code Composer Studio (CCS) Integrated Development Environment (IDE) for Hercules Safety MCUs

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, (...)

IDE, configuration, compiler or debugger

HALCOGEN — Hardware Abstraction Layer Code Generator for Hercules MCUs

HALCoGen allows users to generate hardware abstraction layer device drivers for Hercules™ microcontrollers. HALCoGen provides a graphical user interface that allows the user to configure peripherals, interrupts, clocks, and other Hercules microcontroller parameters. Once the Hercules device (...)
IDE, configuration, compiler or debugger

HET_IDE — High End Timer (HET)

The High-End Timer (HET) is a programmable timer co-processor available on TI’s high-performance Hercules Microcontrollers. The HET enables sophisticated timing functions for real-time control applications. Programming the HET provides an alternate approach to the use of costly FPGAs or ASICs which (...)
IDE, configuration, compiler or debugger

NHET-ASSEMBLER — NHET Assembler Tool

TI's Enhanced High-End Timer (NHET) module provides sophisticated timing functions for real-time control applications.

The NHET Assembler translates programs written in the NHET assembly language into multiple output formats for use in code-generation tools such as TI's Code Composer Studio.
IDE, configuration, compiler or debugger

SAFETI-HALCOGEN-CSP — SafeTI Compliance Support Package for HALCoGen (Hardware Abstraction Layer Code Generator)

The HALCoGen Compliance Support Package (CSP) was developed to provide the necessary documentation, reports and unit test capability to assist customers using HALCoGen generated software to comply with functional safety standards such as IEC 61508 and ISO 26262.

Prerequisites:

The below items are (...)
IDE, configuration, compiler or debugger

SAFETI-HERCULES-DIAG-LIB-CSP — SafeTI Compliance Support Package for Hercules Diagnostic Library

The SafeTI Hercules Diagnostic Library Compliance Support Package (CSP) was developed to provide the necessary documentation and reports to assist customers using the SafeTI Hercules Diagnostic Library to comply with functional safety standards such as IEC 61508 and ISO 26262.
IDE, configuration, compiler or debugger

SAFETI_CQKIT — Safety compiler qualification kit

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
Operating system (OS)

WHIS-3P-MCURTOS — WITTENSTEIN high integrity systems MCU SafeRTOS and OpenRTOS

WITTENSTEIN high integrity systems is an RTOS company that specializes in producing and supplying real-time operating systems and software components to the medical, automotive, aerospace and industrial sectors. WITTENSTEIN’s products support TI’s Hercules™ Arm® Cortex®-R (...)
From: WITTENSTEIN High Integrity Systems
Software programming tool

NOWECC — ECC generation tool

The Hercules microcontroller family contains as part of the embedded flash module a circuit that provides, the capability to detect and correct memory faults. This Single bit Error Correction and Double bit Error Detection circuit (SECDED) needs 8 Error correction check bits for every 64 bit of (...)
Software programming tool

UNIFLASH — UniFlash stand-alone flash tool for microcontrollers, Sitara™; processors and SimpleLink™

Supported devices: CC13xx, CC25xx, CC26xx, CC3x20, CC3x30, CC3x35, Tiva, C2000, MSP43x, Hercules, PGA9xx, IWR12xx, IWR14xx, IWR16xx, IWR18xx , IWR68xx, AWR12xx, AWR14xx, AWR16xx, AWR18xx.  Command line only: AM335x, AM437x, AM571x, AM572x, AM574x, AM65XX, K2G

CCS Uniflash is a standalone tool used (...)

Simulation model

TMS570LS31x ZWT BSDL Model (Rev. A)

SPNM022A.ZIP (11 KB) - BSDL Model
Simulation model

TMS570LS31x4 and TMS570LS21x4 PGE IBIS Models (Silicon Revision B)

SPNM036.ZIP (255 KB) - IBIS Model
Simulation model

TMS570LS31x4 and TMS570LS21x4 PGE IBIS Models (Silicon Revision C)

SPNM037.ZIP (255 KB) - IBIS Model
Simulation model

TMS570LS31x, and TMS570LS21x ZWT IBIS Models (Silicon Revision B)

SPNM042.ZIP (256 KB) - IBIS Model
Simulation model

TMS570LS31x, and TMS570LS21x ZWT IBIS Models (Silicon Revision C)

SPNM043.ZIP (256 KB) - IBIS Model
Calculation tool

FMZPLL_CALCULATOR — FMzPLL Configuration Tool

The FMzPLL Calculator assists a user with the configuration of the FMzPLL on TMS570 microcontrollers. It allows the user to input:
  • OSCIN speed
  • multiplier setting
  • divider settings
  • frequency modulation settings
  • PLL/OSC fail options
Once the user has configured the desired options, the calculator displays (...)
Package Pins Download
LQFP (PGE) 144 View options
NFBGA (ZWT) 337 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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