1. Give PDI access to MII management:

   According to the ESC hardware data sheet, by default MII management control is set only to the ECAT master. PDI has to claim access to MII management via the EtherCAT IP register MII Management PDI Access State (0x0517). This opens the MII management access to PDI. Once this is enabled, the PDI can access the PHY registers via the MII Management Control and PHY Address registers. An example is shown in the following code:

   #define ESC_MII_PDI_ACCESS_OFFSET 0x0517 //0x28B – High for C28x, 0x0517 for CM
   ESC_writeWordISR(0x0100, ESC_MII_ECAT_ACCESS_OFFSET); //0x0100 for C28x, 0x01 for CM

   The ESC base address and offset are different between C28 core and CM (M4) core due to the addressable register length (16-bit for C28 and 8-bit for CM). Since the ESC register is 8-bit, the offset and address using C28 core control needs to be halved.

2. Set PHY address to read or write:

   The ESC register 0x0512 defines the PHY address to be read or write. See the following code:

   #define ESC_PHY_ADDRESS_OFFSET 0x0512 //0x289 – low for C28x, 0x0512 for CM
   ESC_writeWordISR(PHY address, ESC_PHY_ADDRESS_OFFSET);

3. Set the value to write to PHY register (write):

   The ESC register 0x0514:0x0515 defines the PHY data to be read or write to the PHY register. See the following code:

   #define ESC_PHY_DATA_OFFSET 0x0514 //0x28A – low for C28x, 0x0514 for CM
   ESC_writeWordISR(PHY data, ESC_PHY_DATA_OFFSET);

4. Initiate read or write command:

   The ESC register 0x0510:0x0511 defines the MII management control and status. The bit 9:8 defines the commands to read or write the PHY register.

   Bit 9:8 commands:

   00: No command/MI idle (clear error bits)

   01: Read

   10: Write

   11: Reserved/invalid command (do not issue)

   See the following code:

   #define ESC_MII_CTRL_STATUS_1_OFFSET 0x0510 //0x288 – low for C28x, 0x0510 for CM
   #define ESC_MII_CTRL_STATUS_2_OFFSET 0x0511 //0x288 – high for C28x, 0x0511 for CM
   ESC_writeWordISR(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //Write command for C28x
   ESC_writeWordISR(0x0200, ESC_MII_CTRL_STATUS_2_OFFSET); // Write command for CM
   ESC_writeWord(0x0100, ESC_MII_CTRL_STATUS_1_OFFSET); //Read command for C28x
   ESC_writeWord(0x0100, ESC_MII_CTRL_STATUS_2_OFFSET); //Read command for CM

The previously-described approach is to access standard registers 0 to 31 defined in IEEE 802.3. For accessing the clause 45 extended register set, the Register Control Register (REGCR, address 0x000D) and Data Register (ADDAR, address 0x000E) need to be set. Register REGCR [4:0] is the device address DEVAD that directs any accesses of the ADDAR register to the appropriate MDIO manageable device. The following example demonstrates a write operation with no post increment according to the example write operation section of the DP83822 Robust, Low Power 10/100 Mbps Ethernet Physical Layer Transceiver data sheet. In this example, the MAC impedance is adjusted to 99.25 Ω using the IO MUX GPIO Control Register (IOCTRL, address 0x0461).

• Write the value 0x001F to register 0x000D
• Write the value 0x0461 to register 0x000E (Sets desired register to the IOCTRL)
• Write the value 0x401F to register 0x000D
• Write the value 0x0400 to register 0x000E (Sets MAC impedance to 99.25 Ω)

See the code in CCS.

#define ESC_PHY_REG_ADDRESS_OFFSET 0x0513 //0x289 – High for C28x, 0x0513 for CM
#define ESC_PHY_DATA_OFFSET 0x0514 //0x28A – low for C28x, 0x0514 for CM
#define ESC_MII_CTRL_STATUS_1_OFFSET 0x0510 //0x288 – low for C28x, 0x0510 for CM
#define ESC_MII_CTRL_STATUS_2_OFFSET 0x0511 //0x288 – high for C28x, 0x0511 for CM
ESC_writeWordISR(0x0D00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0D for CM, set extended PHY register control
ESC_writeWordISR(0x001F, ESC_PHY_DATA_OFFSET); // DEVAD for MMD
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM
ESC_writeWordISR(0x0E00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0E for CM, set extended PHY Data register
ESC_writeWordISR(0x0461, ESC_PHY_DATA_OFFSET); // PHY extended register address
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM
ESC_writeWordISR(0x0D00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0D for CM, set extended PHY register control
ESC_writeWordISR(0x401F, ESC_PHY_DATA_OFFSET); // change to Data in REGCR Bit 15:14
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM
ESC_writeWordISR(0x0E00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0E for CM, set extended PHY Data register
ESC_writeWordISR(0x0400, ESC_PHY_DATA_OFFSET); // PHY extended register value to be written
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM

To read the extended PHY register, the following example demonstrates a read operation. In this example, the MMD7 Energy Efficient Ethernet Link Partner Ability Register (MMD7_EEE_LP_ABILITY, address 0x703D) is read.

• Write the value 0x0007 to register 0x000D
• Write the value 0x003D to register 0x000E (Sets desired register to the MMD7_EEE_LP_ABILITY)
• Write the value 0x4007 to register 0x000D
• Read the value of register 0x000E (Data read is the value contained within the MMD7_EEE_LP_ABILITY)

See the code in CCS.

#define ESC_PHY_REG_ADDRESS_OFFSET 0x0513 //0x289 – High for C28x, 0x0513 for CM
#define ESC_PHY_DATA_OFFSET 0x0514 //0x28A – low for C28x, 0x0514 for CM
#define ESC_MII_CTRL_STATUS_1_OFFSET 0x0510 //0x288 – low for C28x, 0x0510 for CM
#define ESC_MII_CTRL_STATUS_2_OFFSET 0x0511 //0x288 – high for C28x, 0x0511 for CM
ESC_writeWordISR(0x0D00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0D for CM, set extended PHY register control
ESC_writeWordISR(0x0007, ESC_PHY_DATA_OFFSET); // DEVAD for MMD7
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM
ESC_writeWordISR(0x0E00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0E for CM, set extended PHY Data register
ESC_writeWordISR(0x003D, ESC_PHY_DATA_OFFSET); // PHY extended register address
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM
ESC_writeWordISR(0x0D00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0D for CM, set extended PHY register control
ESC_writeWordISR(0x4007, ESC_PHY_DATA_OFFSET); // change to Data in REGCR Bit 15:14
ESC_writeWord(0x0200, ESC_MII_CTRL_STATUS_1_OFFSET); //write command for C28x, status_2_offset register for CM
ESC_writeWordISR(0x0E00, ESC_PHY_REG_ADDRESS_OFFSET); //0x0E for CM, set extended PHY Data register
ESC_writeWord(0x0100, ESC_MII_CTRL_STATUS_1_OFFSET); //Read command for C28x, status_2_offset register for CM