TMS320F28P650DH

ACTIVE

Product details

TI functional safety category Functional Safety-Compliant Operating temperature range (°C) -40 to 125 Rating Catalog
TI functional safety category Functional Safety-Compliant Operating temperature range (°C) -40 to 125 Rating Catalog
HLQFP (PTP) 176 676 mm² 26 x 26 NFBGA (NMR) 169 81 mm² 9 x 9 NFBGA (ZEJ) 256 169 mm² 13 x 13

Real-time Processing

  • Contains up to three CPUs: two 32-bit C28x DSP CPUs and one CLA CPU, all running at 200 MHz
  • Delivers a total processing power equivalent to 1000-MHz Arm Cortex-M7 based device on real-time signal chain performance (see the Real-time Benchmarks Showcasing C2000™ Control MCU’s Optimized Signal Chain Application Note)
  • C28x DSP architecture
    • IEEE 754 double-precision (64-bit) Floating-Point Unit (FPU)
    • Trigonometric Math Unit (TMU)
    • Fast Integer Division (FINTDIV)
    • CRC engine and instructions (VCRC)
  • Control Law Accelerator (CLA) CPU
    • IEEE 754 single-precision floating-point
    • Executes code independently of C28x CPUs

Memory

  • 1.28MB of CPU-mappable flash (ECC-protected) with 5 flash banks
  • 248KB of RAM (Enhanced Parity-protected)
  • External Memory Interface (EMIF) with ASRAM, SDRAM support or ASIC/FPGA

Analog Subsystem

  • Three Analog-to-Digital Converters (ADCs)
    • 16-bit mode, 1.19 MSPS each
    • 12-bit mode, 3.92 MSPS each
    • Up to 40 single-ended or 19 differential inputs
    • Separate sample-and-hold (S/H) on each ADC to enable simultaneous measurements
    • Hardware post-processing of conversions
    • Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
    • 24 redundant input channels for flexibility
    • Automatic comparison of conversion results for functional safety applications
  • 11 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
    • DAC with slope compensation – enabling peak current and valley current mode control
    • Connection options for internal temperature sensor and ADC reference
  • Two 12-bit buffered DAC outputs

Control Peripherals

  • 36 Pulse Width Modulator (PWM) channels, all with 150-ps high-resolution capability (HRPWM)
    • Minimum Dead-Band Logic (MINDB), Illegal Combo Logic (ICL), and other special features (that is, Diode Emulation [DE]) support
    • Enable Matrix Converters, Multilevel Converters, and Resonant Converters support without additional external logic
  • Seven Enhanced Capture (eCAP) modules
    • High-resolution Capture (HRCAP) available on two of the seven eCAP modules
    • Two new monitor units for edge, pulse width, and period that can be coupled with ePWM strobes and trip events
    • Increased 256 inputs for more capture options
    • New ADC SOC generation capability
    • eCAP can also be used for additional PWM
    • Six Enhanced Quadrature Encoder Pulse (eQEP) modules
    • 16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
    • Embedded Pattern Generator (EPG)
  • Configurable Logic Block
    • Six logic tiles to augment existing peripheral capability or define customized logic to reduce or remove external CPLD/FPGA
    • Supports Encoder interfaces without the need of FPGA
    • Enables customized PWM generation for power conversion

Communications Peripherals

  • EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
  • USB 2.0 (MAC + PHY)
  • Fast Serial Interface (FSI) enabling up to 200Mbps data exchange across isolation
  • Four high-speed (up to 50-MHz) SPI ports
  • Four Serial Communications Interfaces (SCI) (support UART)
  • Two high-speed (25Mbps) Universal Asynchronous Receiver/Transmitters (UARTs)
  • Two I2C interfaces (400Kbps)
  • External boot option via SPI/ SCI/I2C
  • Two UART-compatible Local Interconnect Network (LIN) Modules (support SCI)
  • Power-Management Bus (PMBus) interface (supports I2C)
  • One Controller Area Network (CAN/DCAN)
  • Two CAN FD/MCAN Controller Area Networks with Flexible Data Rate

System Peripherals

  • Two 6-channel Direct Memory Access (DMA) controllers
  • 185 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins
  • Expanded Peripheral Interrupt controller (ePIE)
  • Low-power mode (LPM) support
  • Embedded Real-time Analysis and Diagnostic (ERAD)
  • Background CRC (BGCRC)

Security Peripherals

  • Advanced Encryption Standard (AES-128, 192, 256) accelerator
  • Security
    • JTAGLOCK
    • Zero-pin boot
    • Dual-zone security
  • Unique Identification (UID) number

Safety Peripherals

  • Easier implementation with Reciprocal comparison
  • Lockstep on C28x CPU 2
  • Memory Power-On Self-Test (MPOST)
  • Hardware Built-in Self-Test (HWBIST)
  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 system design
    • Systematic capability up to ASIL D and SIL 3 targeted
    • Hardware capability up to ASIL B and SIL 2 targeted
  • Safety-related certification
    • ISO 26262 and IEC 61508 certification up to ASIL B and SIL 2 by TÜV SÜD planned

Clock and System Control

  • Two internal 10-MHz oscillators
  • On-chip crystal oscillator
  • 2*APLL, BOR, Redundant interrupt vector RAM
  • Windowed watchdog timer module
  • Missing clock detection circuitry
  • Dual-clock Comparator (DCC)
  • Live Firmware Update (LFU)
    • Fast context switching from old to new firmware with or without a power cycle
  • 1.2-V core, 3.3-V I/O design
    • Internal VREG for 1.2-V generation
    • Brownout reset (BOR) circuit

Package options:

  • Lead-free, green packaging
  • 256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEJ suffix], 13 mm × 13 mm/0.8-mm pitch
  • 176-pin PowerPAD™ Thermally Enhanced Low-profile Quad Flatpack (HLQFP) [PTP suffix], 26 mm × 26 mm/0.5-mm pitch
  • 169-ball New Fine Pitch Ball Grid Array (nFBGA) [NMR suffix], 9 mm × 9 mm/0.65-mm pitch
  • 100-pin PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP suffix], 16 mm × 16 mm/0.5-mm pitch

Temperature

  • Ambient (T A ): –40°C to 125°C (industrial and automotive qualified)

Real-time Processing

  • Contains up to three CPUs: two 32-bit C28x DSP CPUs and one CLA CPU, all running at 200 MHz
  • Delivers a total processing power equivalent to 1000-MHz Arm Cortex-M7 based device on real-time signal chain performance (see the Real-time Benchmarks Showcasing C2000™ Control MCU’s Optimized Signal Chain Application Note)
  • C28x DSP architecture
    • IEEE 754 double-precision (64-bit) Floating-Point Unit (FPU)
    • Trigonometric Math Unit (TMU)
    • Fast Integer Division (FINTDIV)
    • CRC engine and instructions (VCRC)
  • Control Law Accelerator (CLA) CPU
    • IEEE 754 single-precision floating-point
    • Executes code independently of C28x CPUs

Memory

  • 1.28MB of CPU-mappable flash (ECC-protected) with 5 flash banks
  • 248KB of RAM (Enhanced Parity-protected)
  • External Memory Interface (EMIF) with ASRAM, SDRAM support or ASIC/FPGA

Analog Subsystem

  • Three Analog-to-Digital Converters (ADCs)
    • 16-bit mode, 1.19 MSPS each
    • 12-bit mode, 3.92 MSPS each
    • Up to 40 single-ended or 19 differential inputs
    • Separate sample-and-hold (S/H) on each ADC to enable simultaneous measurements
    • Hardware post-processing of conversions
    • Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
    • 24 redundant input channels for flexibility
    • Automatic comparison of conversion results for functional safety applications
  • 11 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
    • DAC with slope compensation – enabling peak current and valley current mode control
    • Connection options for internal temperature sensor and ADC reference
  • Two 12-bit buffered DAC outputs

Control Peripherals

  • 36 Pulse Width Modulator (PWM) channels, all with 150-ps high-resolution capability (HRPWM)
    • Minimum Dead-Band Logic (MINDB), Illegal Combo Logic (ICL), and other special features (that is, Diode Emulation [DE]) support
    • Enable Matrix Converters, Multilevel Converters, and Resonant Converters support without additional external logic
  • Seven Enhanced Capture (eCAP) modules
    • High-resolution Capture (HRCAP) available on two of the seven eCAP modules
    • Two new monitor units for edge, pulse width, and period that can be coupled with ePWM strobes and trip events
    • Increased 256 inputs for more capture options
    • New ADC SOC generation capability
    • eCAP can also be used for additional PWM
    • Six Enhanced Quadrature Encoder Pulse (eQEP) modules
    • 16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
    • Embedded Pattern Generator (EPG)
  • Configurable Logic Block
    • Six logic tiles to augment existing peripheral capability or define customized logic to reduce or remove external CPLD/FPGA
    • Supports Encoder interfaces without the need of FPGA
    • Enables customized PWM generation for power conversion

Communications Peripherals

  • EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
  • USB 2.0 (MAC + PHY)
  • Fast Serial Interface (FSI) enabling up to 200Mbps data exchange across isolation
  • Four high-speed (up to 50-MHz) SPI ports
  • Four Serial Communications Interfaces (SCI) (support UART)
  • Two high-speed (25Mbps) Universal Asynchronous Receiver/Transmitters (UARTs)
  • Two I2C interfaces (400Kbps)
  • External boot option via SPI/ SCI/I2C
  • Two UART-compatible Local Interconnect Network (LIN) Modules (support SCI)
  • Power-Management Bus (PMBus) interface (supports I2C)
  • One Controller Area Network (CAN/DCAN)
  • Two CAN FD/MCAN Controller Area Networks with Flexible Data Rate

System Peripherals

  • Two 6-channel Direct Memory Access (DMA) controllers
  • 185 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins
  • Expanded Peripheral Interrupt controller (ePIE)
  • Low-power mode (LPM) support
  • Embedded Real-time Analysis and Diagnostic (ERAD)
  • Background CRC (BGCRC)

Security Peripherals

  • Advanced Encryption Standard (AES-128, 192, 256) accelerator
  • Security
    • JTAGLOCK
    • Zero-pin boot
    • Dual-zone security
  • Unique Identification (UID) number

Safety Peripherals

  • Easier implementation with Reciprocal comparison
  • Lockstep on C28x CPU 2
  • Memory Power-On Self-Test (MPOST)
  • Hardware Built-in Self-Test (HWBIST)
  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 system design
    • Systematic capability up to ASIL D and SIL 3 targeted
    • Hardware capability up to ASIL B and SIL 2 targeted
  • Safety-related certification
    • ISO 26262 and IEC 61508 certification up to ASIL B and SIL 2 by TÜV SÜD planned

Clock and System Control

  • Two internal 10-MHz oscillators
  • On-chip crystal oscillator
  • 2*APLL, BOR, Redundant interrupt vector RAM
  • Windowed watchdog timer module
  • Missing clock detection circuitry
  • Dual-clock Comparator (DCC)
  • Live Firmware Update (LFU)
    • Fast context switching from old to new firmware with or without a power cycle
  • 1.2-V core, 3.3-V I/O design
    • Internal VREG for 1.2-V generation
    • Brownout reset (BOR) circuit

Package options:

  • Lead-free, green packaging
  • 256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEJ suffix], 13 mm × 13 mm/0.8-mm pitch
  • 176-pin PowerPAD™ Thermally Enhanced Low-profile Quad Flatpack (HLQFP) [PTP suffix], 26 mm × 26 mm/0.5-mm pitch
  • 169-ball New Fine Pitch Ball Grid Array (nFBGA) [NMR suffix], 9 mm × 9 mm/0.65-mm pitch
  • 100-pin PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP suffix], 16 mm × 16 mm/0.5-mm pitch

Temperature

  • Ambient (T A ): –40°C to 125°C (industrial and automotive qualified)

The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies.

These include such applications as:

The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 200 MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400-MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, the Control Law Accelerator (CLA) enables an additional 200 MIPS per core of independent processing ability. This is equivalent to the 280-MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core).

The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x.

High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features.

The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU.

An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. The Fast Serial Interface (FSI) enables up to 200 Mbps of robust communications across an isolation boundary.

As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot.

From a safety standpoint, F28P65x supports numerous safety enablers. For more details, see Industrial Functional Safety for C2000™ Real-Time Microcontrollers and Automotive Functional Safety for C2000™ Real-Time Microcontrollers.

Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page.

The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered.

Ready to get started? Check out the TMDSCNCD28P65X evaluation board and download C2000Ware.

The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies.

These include such applications as:

The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 200 MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400-MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, the Control Law Accelerator (CLA) enables an additional 200 MIPS per core of independent processing ability. This is equivalent to the 280-MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core).

The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x.

High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features.

The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU.

An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. The Fast Serial Interface (FSI) enables up to 200 Mbps of robust communications across an isolation boundary.

As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot.

From a safety standpoint, F28P65x supports numerous safety enablers. For more details, see Industrial Functional Safety for C2000™ Real-Time Microcontrollers and Automotive Functional Safety for C2000™ Real-Time Microcontrollers.

Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page.

The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered.

Ready to get started? Check out the TMDSCNCD28P65X evaluation board and download C2000Ware.

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Technical documentation

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Type Title Date
* Data sheet TMS320F28P65x Real-Time Microcontrollers datasheet (Rev. B) PDF | HTML 17 Nov 2023
* Errata TMS320F28P65x Real-Time MCUs Silicon Errata (Rev. C) PDF | HTML 19 Mar 2024
* User guide TMS320F28P65x Real-Time Microcontrollers Technical Reference Manual (Rev. A) 02 Dec 2023
Application note EEPROM Emulation for Generation 3 C2000 Real-Time Controllers (Rev. A) PDF | HTML 12 Apr 2024
Application note Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs (Rev. A) PDF | HTML 12 Jan 2024
Application note EEPROM Emulation for Gen 3 C2000 Real-Time MCUs PDF | HTML 16 Nov 2023
Cybersecurity advisory C2000 DCSM ROM Gadget/ROP Vulnerability PDF | HTML 13 Nov 2023
Product overview Industrial Functional Safety for C2000™ Real-Time Microcontrollers (Rev. D) 08 Nov 2023
Product overview Implementing IEC 60730 / UL 1998 Compliance for C2000 Real-Time Microcontrollers PDF | HTML 12 Oct 2023
User guide Migration Between TMS320F2837x and TMS320F28P65x PDF | HTML 02 Aug 2023
User guide Migration Between TMS320F2838x and TMS320F28P65x PDF | HTML 31 Jul 2023
White paper Achieving High Efficiency and Enabling Integration in EV Powertrain Subsystems (Rev. A) PDF | HTML 17 Jul 2023
Application note CRC Engines in C2000 Devices (Rev. A) PDF | HTML 01 May 2023
Application note ADC Input Circuit Evaluation for C2000 MCUs (using TINA-TI simulation tool) (Rev. A) PDF | HTML 24 Mar 2023
Application note ADC Input Circuit Evaluation for C2000 Real-Time MCUs (using PSPICE-FOR-TI) PDF | HTML 24 Mar 2023
Application note Charge-Sharing Driving Circuits for C2000 ADCs (using PSPICE-FOR-TI) (Rev. A) PDF | HTML 24 Mar 2023
Application note Charge-Sharing Driving Circuits for C2000 ADCs (using TINA-TI simulation tool) (Rev. A) PDF | HTML 24 Mar 2023
Application note Methods for Mitigating ADC Memory Cross-Talk (Rev. A) PDF | HTML 24 Mar 2023
Application note Using SMI of C2000 EtherCAT Slave Controller for Ethernet PHY Configuration PDF | HTML 27 Feb 2023
Application note C2000 ePWM Developer’s Guide (Rev. A) PDF | HTML 24 Feb 2023
Application note How to Implement Custom Serial Interfaces Using Configurable Logic Block (CLB) PDF | HTML 03 Feb 2023
Application note C2000 SysConfig Linker Command Tool PDF | HTML 26 Jan 2023
Application note Using the Fast Serial Interface (FSI) With Multiple Devices in an Application (Rev. E) PDF | HTML 25 Jan 2023
Application note Diagnosing Delta-Sigma Modulator Bitstream Using C2000™ Configurable Logic Block PDF | HTML 19 Dec 2022
Application note Software Examples to Showcase Unique Capabilities of TI’s C2000™ CLA (Rev. A) PDF | HTML 17 Nov 2022
User guide Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) (Rev. C) PDF | HTML 29 Jun 2022
Application note Implement three-phase interleaved LLC on C2000 Type-4 PWM PDF | HTML 30 Mar 2022
Application note The Essential Guide for Developing With C2000 Real-Time Microcontrollers (Rev. F) PDF | HTML 03 Mar 2022
Application note Real-Time Benchmarks Showcasing C2000™ Control MCU's Optimized Signal Chain (Rev. A) PDF | HTML 15 Dec 2021
Application note Achieve Delayed Protection for Three-Level Inverter With Type 4 EPWM PDF | HTML 29 Oct 2021
Application note C2000 SysConfig PDF | HTML 20 Oct 2021
Application note Getting Started with the MCAN (CAN FD) Module PDF | HTML 20 Oct 2021
Application note Achieve Delayed Protection for Three-Level Inverter With CLB PDF | HTML 28 Jun 2021
Application note Programming Examples for the DCAN Module (Rev. A) PDF | HTML 20 May 2021
Application note Leverage New Type ePWM Features for Multiple Phase Control PDF | HTML 11 May 2021
Application note C2000™ DCSM Security Tool (Rev. A) PDF | HTML 10 May 2021
White paper TI GaN FET와 C2000™ 실시간 MCU를 결합하여 전력 밀도가 높고 효율적인 전원 시스템 달성 18 Mar 2021
White paper 結合 TI GaN FETs 與 C2000™ 即時 MCU,實現功率密集與有效率的數位電源系統 18 Mar 2021
Application note CRM/ZVS PFC Implementation Based on C2000 Type-4 PWM Module PDF | HTML 18 Feb 2021
White paper Achieve Power-Dense and Efficient Digital Power Systems by Combining TI GaN FETs 05 Jan 2021
More literature Maximize density, power, and reliability with TI GaN and C2000™ real-time MCUs 15 Dec 2020
Application note C2000™ Unique Device Number (Rev. B) PDF | HTML 17 Sep 2020
Application note Secure BOOT On C2000 Device 21 Jul 2020
Application note How to Migrate Custom Logic From an FPGA/CPLD to C2000 Microcontrollers (Rev. A) 15 Jun 2020
Application note Enhancing Device Security by Using JTAGLOCK Feature PDF | HTML 27 May 2020
E-book Ein Techniker-Leitfaden für Industrieroboter-Designs 25 Mar 2020
Application note EtherCAT Based Connected Servo Drive using Fast Current Loop on PMSM (Rev. B) PDF | HTML 19 Feb 2020
White paper Distributed Power Control Architecture w/ C2000 MCUs Over Fast Serial Interface PDF | HTML 14 Feb 2020
E-book E-book: An engineer’s guide to industrial robot designs 12 Feb 2020
Application note Configurable Error Generator for Controller Area Network PDF | HTML 19 Dec 2019
User guide TMS320C28x Extended Instruction Sets Technical Reference Manual (Rev. C) 29 Oct 2019
Application note Leveraging High Resolution Capture (HRCAP) for Single Wire Data Transfer PDF | HTML 28 Aug 2019
Application note Development Tool Versions for C2000 Support 19 Jul 2019
Application note Fast Integer Division – A Differentiated Offering From C2000 Product Family PDF | HTML 14 Jun 2019
Application note Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 07 May 2019
Application note Embedded Real-Time Analysis and Response for Control Applications PDF | HTML 29 Mar 2019
Application note Designing With The C2000 Configurable Logic Block 05 Feb 2019
Application note MSL Ratings and Reflow Profiles (Rev. A) 13 Dec 2018
Application note Fast Serial Interface (FSI) Skew Compensation 08 Nov 2018
White paper Maximizing power for Level 3 EV charging stations 12 Jun 2018
User guide TMS320C28x DSP CPU and Instruction Set (Rev. F) 10 Apr 2015
Application note Calculating FIT for a Mission Profile 24 Mar 2015
User guide C2000 Real-Time Control Peripheral Reference Guide (Rev. S) PDF | HTML 30 Aug 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LAUNCHXL-F28P65X — C2000™ real-time MCU F28P65x LaunchPad™ development kit

LAUNCHXL-F28P65X is a low-cost development board for TI C2000™ real-time microcontrollers series of F28P65x devices. Ideal for initial evaluation and prototyping, it provides a standardized and easy to use platform to develop your next application. This extended version LaunchPad™ (...)

User guide: PDF | HTML
Not available on TI.com
IDE, configuration, compiler or debugger

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

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HLQFP (PTP) 176 View options
NFBGA (NMR) 169 View options
NFBGA (ZEJ) 256 View options

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