SPRADM6 December   2024 AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Load Binaries to AM62D
  5. 2Processor Core Benchmarks
    1. 2.1 C7x DSP Benchmark
      1. 2.1.1 Fast Fourier Transform
      2. 2.1.2 Digital Signal Processing
        1. 2.1.2.1 FIR
        2. 2.1.2.2 Cascade Biquad
        3. 2.1.2.3 Dot Product
      3. 2.1.3 Mathematical Operations
    2. 2.2 Dhrystone on A53 cores
  6. 3Memory System Benchmarks
    1. 3.1 Critical Memory Access Latency
    2. 3.2 UDMA: DDR to DDR Data Copy
    3. 3.3 C7x DRU Performance: Block Copy with DMA
  7. 4Application Specific Benchmarks
    1. 4.1 SBL Boot Time
    2. 4.2 IPC Performance
    3. 4.3 Flash
    4. 4.4 Application Specific Latency
  8. 5Summary
  9. 6References

4.1 SBL Boot Time

The SBL setup details are shown in Table 4-1.

Table 4-1 SBL Setup Details

Property

Detail
Software or application used sbl_ospi_multistage, ipc_rpmsg_echo, and HSM App Images
Cores booted by stage1 SBL r5f0-0
Cores booted by stage2 SBL hsm-m4f0-0 mcu-r5f0-0 a530-0 c75ss0
Size of image loaded by stage1: r5f0-0 199KB
Size of HSM-M4F image loaded by stage2 7.81KB
Size of MCU-R5F image loaded by stage2 39.06KB
Size of a53 image loaded by stage 2 73.92KB
Size of C7x image loaded by stage 2 144.82KB
Total size of images loaded by stage2 144.82KB

The boot times for stage1 and stage2 using both OSPI and EMMC on HS-FS device are shown in Table 4-1. Note that most of time in Stage1 is attributed to DDR initialization.

Table 4-2 SBL Boot Time

Stage

OSPI at 166.667MHz [ms]

EMMC at 200.0MHz [ms]

Stage1

40.861

63.044

Stage2

33.912

52.372