SPRADM6 December   2024 AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Load Binaries to AM62D
  5. 2Processor Core Benchmarks
    1. 2.1 C7x DSP Benchmark
      1. 2.1.1 Fast Fourier Transform
      2. 2.1.2 Digital Signal Processing
        1. 2.1.2.1 FIR
        2. 2.1.2.2 Cascade Biquad
        3. 2.1.2.3 Dot Product
      3. 2.1.3 Mathematical Operations
    2. 2.2 Dhrystone on A53 cores
  6. 3Memory System Benchmarks
    1. 3.1 Critical Memory Access Latency
    2. 3.2 UDMA: DDR to DDR Data Copy
    3. 3.3 C7x DRU Performance: Block Copy with DMA
  7. 4Application Specific Benchmarks
    1. 4.1 SBL Boot Time
    2. 4.2 IPC Performance
    3. 4.3 Flash
    4. 4.4 Application Specific Latency
  8. 5Summary
  9. 6References

2.1.2.2 Cascade Biquad

The DSPLIB_cascadeBiquad implements multichannel multistage cascade on input data. Table 2-4 shows performance results of implementing 32 channels cascade biquad on float input vectors. The table also shows performance improvments compared to older C66x DSP.

Table 2-4 Cascade Biquad Performance on C7x DSP

Data Type

Data Size

Num Channels

Num Stages

EVM Cycles

Cycles/Biquad

C66x to C7x Improvement

Float

512

32

3

14772

0.3

4.57x

Float

128

32

7

8494

0.3

7.46x