SPRADM6 December   2024 AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Load Binaries to AM62D
  5. 2Processor Core Benchmarks
    1. 2.1 C7x DSP Benchmark
      1. 2.1.1 Fast Fourier Transform
      2. 2.1.2 Digital Signal Processing
        1. 2.1.2.1 FIR
        2. 2.1.2.2 Cascade Biquad
        3. 2.1.2.3 Dot Product
      3. 2.1.3 Mathematical Operations
    2. 2.2 Dhrystone on A53 cores
  6. 3Memory System Benchmarks
    1. 3.1 Critical Memory Access Latency
    2. 3.2 UDMA: DDR to DDR Data Copy
    3. 3.3 C7x DRU Performance: Block Copy with DMA
  7. 4Application Specific Benchmarks
    1. 4.1 SBL Boot Time
    2. 4.2 IPC Performance
    3. 4.3 Flash
    4. 4.4 Application Specific Latency
  8. 5Summary
  9. 6References

IPC Performance

The IPC notify performance is benchmarked by sending 10,000 notifications among the various processing cores while measuring the latency. All cores are running from DDR with the exception of MCU-R5 from MSRAMTable 4-3 shows the average notify latency.

Table 4-3 IPC Message Notify Latency

Local Core

Remote Core

Average Message Latency [ns]

mcu-r5f0-0

c75ss0

2094ns

mcu-r5f0-0

a530-0

1169ns

mcu-r5f0-0

r5f0-0

1689ns

a530-0

c75ss0

2082ns

c75ss0

r5f0-0

2065ns

a530-0

r5f0-0

1000ns

The IPC RPMSG performance is benchmarked by sending 1000 messages between processors while measuring message latency. Table 4-4shows the average and maximum message latency for various message sizes.

Table 4-4 IPC Message Transfer Latency

Local Core

Remote Core

Message Size

Average Message Latency [µs]

Max Latency [µs]

r5f0-0

a530-0

4

6.842

10

r5f0-0

mcu-r5f0-0

4

8.933

12

r5f0-0

c75ss0

4

79.916

94

r5f0-0

a530-0

32

9.659

12

r5f0-0

a530-0

64

12.655

15

r5f0-0

a530-0

112

17.544

21

r5f0-0

mcu-r5f0-0

32

15.526

18

r5f0-0

mcu-r5f0-0

64

22.628

25

r5f0-0

mcu-r5f0-0

112

33.379

36

r5f0-0

c75ss0

32

89.926

104

r5f0-0

c75ss0

64

92.618

127

r5f0-0

c75ss0

112

113.281

128