2 Potential Risks with Traditional PWM Configuration

Figure 2-1 shows a basic totem pole PFC structure. In Optimized Control Schemes for Totem Pole PFC with Digital Controller, the document discusses the control configurations for the continuous-conduction mode (CCM) control with fixed switching frequency. TCM control requires more complicated logic design for variable switching frequencies.

To achieve ZVS to improve power efficiency, the TCM totem pole PFC relies on an inductor current zero crossing event to implement cycle by cycle control. Normally, external ZCD circuits are required for the inductor current. For a single phase totem pole PFC as shown in Figure 2-1, the high frequency FETs (Q1 and Q2) alternately work as a PFC active FET or sync FET, while slow frequency FETs (Q3 and Q4) switch at grid frequency.

Figure 2-2 shows a common PWM configuration logic with C2000 as an example of positive cycle operation. When the AC input voltage is high (specifically if the input voltage larger than half of the PFC output voltage), generating extra negative inductor current so that switch node voltage discharges to 0V is required to achieve ZVS. According to Figure 2-2, several key configurations are summarized in the following steps.

1. ZCD signal (rising edge) is used to generate the synchronized event to reset the PWM counter.
2. Action qualifier (AQ) submodule setting:
   1. PWM for active FET: set high at CTR results in a zero event. Clear low at CTR results in a CMPA event.
   2. PWM for sync FET: set high at CTR results in a CMPB event. Clear low at CTR results in a zero event
3. Dead band (DB) submodule setting:
   1. Enable the rising edge delay for the active FET PWM and the falling edge delay for the sync FET PWM.

With the configurations shown, the two dead times between the active FET and the sync FET must be defined carefully, which means that the rising edge delay value must be always larger than the falling edge delay value, and the CMPB value must be always larger than the CMPA value. During normal operation, the duration of the negative current is controlled by the rising edge delay value, while the duty cycle is calculated by the CMPA value. These four registers are required to calculate and change in every control loop processing cycle. Updating all the registers at the same time is critical. Otherwise, this can cause disastrous short circuit issues during the power stage.

Theoretically, the global load and one-shot load scheme in the Type-4 EPWM are designed to make sure multiple PWM registers update at the same global event. However, when the register update frequency (which is normally the same as the control loop ISR frequency) is higher than the switching frequency, asynchronous update risks for multiple PWM registers can occur. The detailed root cause and workarounds can be found in Handling PWM Challenges in Resonant Converters. However, the current workarounds do not apply for the TCM totem pole PFC control, since it is required to determine when to update the registers based on the present switching period. Since the switching period is decided by the hardware events for TCM control, the switching periods are unable to be predicted in advance.