3 PWM Configurations for Robust Control

A PWM configuration logic as shown in Figure 3-1 addresses the risks in traditional configurations . Key configurations are highlighted in the following steps:

1. The falling edge of sync FET with additional delay (highlighted in green) is used to reset the PWM counter. This delay represents the dead time of two FETs.
2. AQ submodule setting:
   1. ZCD signal (rising edge) is configured as a T1 event
   2. PWM for active FET: set high at CTR results in a zero event; clear low at CTR results in a CMPA event
   3. PWM for sync FET: set high at CTR results in a CMPA event; clear low at T1 event
3. DB submodule setting:
   1. Enable both rising edge delay and falling edge delay for the sync FET PWM. The rising edge delay represents the dead time of two FETs, while the falling edge delay defines the duration of the negative inductor current.

In this way, the two dead times between active FET and sync FET are decided by a single register separately, which completely avoids shoot through issues because of overlapping registers. Only the falling edge delay and CMPA registers are required to be updated during normal operation.

The following sections describe the details on how to configure the PWM logic.