The falling edge of sync FET PWM is defined as a DCxEVT1 event (active low), through input XBAR, EPWM XBAR and digital compare (DC) submodule, since a DCxEVT1 event can be used to generate a synchronization event for the PWM counter. Figure 3-2 shows how the edge filter function inside the DC submodule is leveraged to create additional delay for a DCxEVT1 event, as shown in the following steps.

1. Select a DCxEVT1 event as the input to the edge filter block.
2. Enable valley capture mode (VCAPCTL[VCAPE])
3. Select CTR = Zero to restart the edge filter (VCAPCTL[TRIGSEL])
4. Configure the edge filter to capture one edge (DCFCTL[EDGECOUNT])
5. Enable the configure for the required delay for the DCxEVT1 signal (SWVDELVAL), which represents the additional delay for the PWM counter sync event.

EPWM_setDigitalCompareFilterInput (base, EPWM_DC_WINDOW_SOURCE_DCAEVT1);
EPWM_enableDigitalCompareEdgeFilter(base);
EPWM_enableValleyCapture(base);
EPWM_setValleyTriggerSource(base, EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO);
EPWM_setDigitalCompareEdgeFilterEdgeCount(base, EPWM_DC_EDGEFILT_EDGECNT_1);
   EPWM_enableValleyHWDelay(base);
EPWM_setValleySWDelayValue(base, 30);

Considering the dead time is relatively stable across operation conditions, it is safe even though the SWVDELVAL register does not operate in shadow mode. Since the active FET and sync FET roles are exchanged under a positive cycle and a negative cycle, the source (sync FET PWM) for the DCxEVT1 event is required to change at the same time. This is accomplished by selecting different GPIOs as the source of the input XBAR.