For each of the parameters, click on the ? to learn about the description.

Description for Figure 4-2:

1. Flash Device: Choose custom flash if the flash is not one of the default flashes on the TI EVM.
2. Flash Name: Write the name of the flash in use, for example, W25Q512JV.
3. Protocol: Choose one of the listed protocols which the flash also supports. This configures the number of lines to be used for Command, Address and Data respectively. It also specifies the data rate, that is DDR (Dual Data Rate) or SDR (Single Data Rate). For example, 4S-4D-4D, means 4 lines is used for Command, Address and Data respectively. For Command the data is latched on either of rising/falling edge, but for Address and Data, the data is latched on both the rising and falling edges.

Description for Figure 4-3:

1. Flash JEDEC Manufacture ID: This value is the same across a specific manufacturer.
2. Flash JEDEC Device ID: This value varies across the same manufacturer's flash variant. For example, a Winbond flash has different device ID for flashes which operate in 1.8V and 3.6V respectively. There are other parameters as well on which the flash part varies and can be found under the flash datasheet.
3. Dummy Clocks (CMD) and Dummy Clocks (READ): Dummy Clocks is used to synchronize flash reads. These values can be obtained from the flash datasheet as well. Look out for sections named as Dummy Cycles/Dummy Clocks. Please note, this field specifies the value which is set at OSPI Controller's end. To set dummy cycle/clock value at flash's end, the flash configuration register needs to be written to. Please refer to the Dummy Cycle Configuration field.
4. Quad Enable Type: Some QSPI flashes have a QE (Quad Enable) bit. This bit needs to be enabled, for protocols like 1S-1S-4S, 4S-4S-4S and 4S-4D-4D.
5. QPI Sequence and OPI Sequence: To enable 4-4-4 mode and 8-8-8 mode respectively, these fields are used.
6. For Flash's Block Size and Sector Size, refer to the flash datasheet. The commands for the same can be obtained from the diagnostics log, but always good to verify from the datasheet.
7. SysConfig allows users to set Sector Size and Block Size, in case the flash supports different sector/block sizes, user can specify certain sector/block size based on the application.
8. The (3B) and (4B) refers to 3 byte and 4 byte addressing mode of the flash. Basically, this specifies how many address bytes must be sent. For a Flash which is less than 16 MB, only 3 bytes addressing is enough to cater to the entire flash region.

Description for Figure 4-4:

1. Protocol Configuration: Protocol usually specifies the number of lines to be used for command, address and data. For the flash to operate in a specific protocol, this section needs to be filled up.
2. Dummy Cycle Configuration: For the flash to operate in a certain protocol, the flash configuration register needs dummy cycles to be configured. This is the flash's side setting and the OSPI Controller's setting is defined under the field Dummy Clocks (READ).
3. STR/DTR Configuration: This can be set to make the flash operate in SDR/DDR mode.

Description for Figure 4-5:

Let's understand this carefully. Suppose the value of a configuration register is 10111101b. If the bits[5:2], needs to be updated with 1001b then, the values in Data Shift Bits, Data Binary Mask and Data To Be Written will be 2, 0x3C and 9 respectively. On the original value 10111101b, mask operation is carried, with the logic (value & ~(Data Binary Mask)). This results in the value being 10000001b. Now the shift operation will be performed as (value | (Data To Be Written << Data Shift Bits)). The final value becomes 10100101b and hence gets written to the configuration register.

Description for Figure 4-6:

Fields are self-explanatory. Flash datasheet can be referred to set the correct values.

Description for Figure 4-7:

All of these values can be found in the Flash Datasheet. Refer to the Read Device ID/Read Manufacture ID Transaction Table from the flash datasheet.

Description for Figure 4-8:

1. WIP Bit and WEL Bit: These bits refer to Write in progress and Write Enable Latch bits in the Flash Status Register.
2. Four Byte Addressing: As explained earlier, this is needed if the flash is of size > 16MB, and it supports specific commands for (4B) addressing.
3. Command Extension Type: Assume the command to be sent is 0x9F. So, in case of:
   1. NONE, 0x9F is sent.
   2. REPEAT: 0x9F, 0x9F is sent.
   3. INVERSE: 0x9F, 0x60 (Inverse of 0x9F) is sent.
4. Quirks Function is used to define a custom API, which performs additional changes to the configuration register of the flash. Currently, this is defined as Flash_quirkSpansionUNHYSADisable. This function basically disables the Hybrid mode of the flash(S28HS512T) present on the TI EVM.