SPRUIG3C January   2018  – August 2019 TDA4VM , TDA4VM-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Related Documentation
    3.     Trademarks
  2. 1Overview and Scope
    1. 1.1 Comparing VCOP and C7000
    2. 1.2 About this Document
      1. 1.2.1 Documentation Conventions
    3. 1.3 Output Format
    4. 1.4 Data Types
      1. 1.4.1 40-bit Incompatibilities
      2. 1.4.2 40-Bit Detection in Host Emulation Mode
    5. 1.5 SIMD Width
    6. 1.6 VCOP Virtual Machine
  3. 2Kernel API
    1. 2.1 Overview
    2. 2.2 Parameter Block
      1. 2.2.1 Tvals Structure
      2. 2.2.2 Pblock Manipulation
  4. 3Loop Control
    1. 3.1 Overview
    2. 3.2 Loop Control and Nested Loops
    3. 3.3 Repeat Loops
    4. 3.4 Compound Conditions
    5. 3.5 Early Exit
  5. 4Addressing
    1. 4.1 Overview
    2. 4.2 Streaming Engines
    3. 4.3 Streaming Address Generators
    4. 4.4 Indexed Addressing
    5. 4.5 Circular Addressing
  6. 5Operations
    1. 5.1 Load Operations
    2. 5.2 Store Operations
      1. 5.2.1 Predicated Stores
      2. 5.2.2 Scatter and Transposing Stores
      3. 5.2.3 Optimization of OFFSET_NP1-Based Transpose
      4. 5.2.4 Rounding Stores
      5. 5.2.5 Saturating Stores
    3. 5.3 Arithmetic Operations
      1. 5.3.1 Vector Compares
      2. 5.3.2 Multiplication with Rounding, Truncation, or Left Shift
    4. 5.4 Lookup and Histogram Table Operations
      1. 5.4.1 Determination of Table Size
      2. 5.4.2 Table Configuration
      3. 5.4.3 Copy-in Operation
      4. 5.4.4 Copy-out Operation
      5. 5.4.5 Index Adjustment from Non-zero Agen
      6. 5.4.6 Lookup Operation
      7. 5.4.7 Histogram Update Operation
      8. 5.4.8 16-Way Lookup and Histogram
  7. 6Performance
    1. 6.1 Overview
    2. 6.2 Compiler Requirements
    3. 6.3 Automatic Performance Profiling
    4. 6.4 Performance Options
  8.   A Warnings and Notes
    1.     A.1 Compatibility Warnings
    2.     A.2 Efficiency Warnings

Loop Control and Nested Loops

As generated, each loop level requires computation to control the loop: initialization of the LCV outside the loop, and an increment, compare, and branch inside the loop. The compiler and ISA provide a handful of mechanisms to reduce or eliminate this overhead.

First, the compiler typically converts simple counting loops to count down rather than up, slightly reducing the cost of the compare and branch operation.

Second, if the body of a loop consists entirely of another loop, the compiler can collapse the two loops into a single loop whose trip count is the product of the original loops.

Finally, and most significantly, the compiler can leverage an ISA feature called the Nested Loop Controller (NLC), which provides hardware loop control similar to VCOP for up to two levels of loop nesting.

The NLC allows loops to be collapsed even if the outer loop has code in addition to the inner loop, by providing automatically-generated predicates for the outer loop code.

The combination of the compiler’s collapsing and the NLC reduce loop control overhead to an acceptable degree. Virtually all kernels should have at least the two inner levels collapsed and controlled by the NLC. Often there are at least two levels that the compiler can collapse, so most loops execute as either singly nested loops, or in rare cases, doubly or triply nested loops. This is important because the C7x relies on software pipelining for performance, and only the inner loop can be pipelined.