SPRUIX1B October   2022  – April 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.4.4  Power-On Reset (POR)
      5. 3.4.5  Brown-Out-Reset (BOR)
      6. 3.4.6  Debugger Reset (SYSRS)
      7. 3.4.7  Simulate CPU Reset
      8. 3.4.8  Watchdog Reset (WDRS)
      9. 3.4.9  NMI Watchdog Reset (NMIWDRS)
      10. 3.4.10 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 Software-Forced Error
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
          1. 3.7.1.1.1 External Resistor (ExtR) Mode
            1. 3.7.1.1.1.1 INTOSC2 with External Precision Resistor – ExtR
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 Auxiliary Clock Input (AUXCLKIN)
        4. 3.7.1.4 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CAN Bit Clock
        6. 3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Using an External Resistor (ExtR) With Internal Oscillator
      10. 3.7.10 Choosing PLL Settings
      11. 3.7.11 System Clock Setup
      12. 3.7.12 SYS PLL Bypass
      13. 3.7.13 Clock (OSCCLK) Failure Detection
        1. 3.7.13.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1 Dedicated RAM (Mx RAM)
        2. 3.11.1.2 Local Shared RAM (LSx RAM)
        3. 3.11.1.3 Access Protection
          1. 3.11.1.3.1 CPU Fetch Protection
          2. 3.11.1.3.2 CPU Write Protection
          3. 3.11.1.3.3 CPU Read Protection
        4. 3.11.1.4 Memory Error Detection, Correction, and Error Handling
          1. 3.11.1.4.1 Error Detection and Correction
          2. 3.11.1.4.2 Error Handling
        5. 3.11.1.5 Application Test Hooks for Error Detection and Correction
        6. 3.11.1.6 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 System Control Register Configuration Restrictions
    14. 3.14 Software
      1. 3.14.1 SYSCTL Examples
        1. 3.14.1.1 Missing clock detection (MCD)
        2. 3.14.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.14.2 TIMER Examples
        1. 3.14.2.1 CPU Timers
        2. 3.14.2.2 CPU Timers
      3. 3.14.3 MEMCFG Examples
        1. 3.14.3.1 Correctable & Uncorrectable Memory Error Handling
      4. 3.14.4 INTERRUPT Examples
        1. 3.14.4.1 External Interrupts (ExternalInterrupt)
        2. 3.14.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.14.4.3 CPU Timer Interrupt Software Prioritization
        4. 3.14.4.4 EPWM Real-Time Interrupt
      5. 3.14.5 LPM Examples
        1. 3.14.5.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
        2. 3.14.5.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
        3. 3.14.5.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
        4. 3.14.5.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
        5. 3.14.5.5 Low Power Modes: Halt Mode and Wakeup using GPIO
        6. 3.14.5.6 Low Power Modes: Halt Mode and Wakeup
      6. 3.14.6 WATCHDOG Examples
        1. 3.14.6.1 Watchdog
    15. 3.15 System Control Registers
      1. 3.15.1  SYSCTRL Base Address Table
      2. 3.15.2  ACCESS_PROTECTION_REGS Registers
      3. 3.15.3  CLK_CFG_REGS Registers
      4. 3.15.4  CPU_SYS_REGS Registers
      5. 3.15.5  CPUTIMER_REGS Registers
      6. 3.15.6  DEV_CFG_REGS Registers
      7. 3.15.7  MEM_CFG_REGS Registers
      8. 3.15.8  MEMORY_ERROR_REGS Registers
      9. 3.15.9  NMI_INTRUPT_REGS Registers
      10. 3.15.10 PIE_CTRL_REGS Registers
      11. 3.15.11 SYNC_SOC_REGS Registers
      12. 3.15.12 SYS_STATUS_REGS Registers
      13. 3.15.13 TEST_ERROR_REGS Registers
      14. 3.15.14 UID_REGS Registers
      15. 3.15.15 WD_REGS Registers
      16. 3.15.16 XINT_REGS Registers
      17. 3.15.17 Register to Driverlib Function Mapping
        1. 3.15.17.1 ASYSCTL Registers to Driverlib Functions
        2. 3.15.17.2 CPUTIMER Registers to Driverlib Functions
        3. 3.15.17.3 MEMCFG Registers to Driverlib Functions
        4. 3.15.17.4 NMI Registers to Driverlib Functions
        5. 3.15.17.5 PIE Registers to Driverlib Functions
        6. 3.15.17.6 SYSCTL Registers to Driverlib Functions
        7. 3.15.17.7 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Memory Maps
        1. 4.7.5.1 Boot ROM Memory Maps
        2. 4.7.5.2 Reserved RAM Memory Maps
      6. 4.7.6  ROM Tables
      7. 4.7.7  Boot Modes and Loaders
        1. 4.7.7.1 Boot Modes
          1. 4.7.7.1.1 Flash Boot
          2. 4.7.7.1.2 RAM Boot
          3. 4.7.7.1.3 Wait Boot
        2. 4.7.7.2 Bootloaders
          1. 4.7.7.2.1 SCI Boot Mode
          2. 4.7.7.2.2 SPI Boot Mode
          3. 4.7.7.2.3 I2C Boot Mode
          4. 4.7.7.2.4 Parallel Boot Mode
          5. 4.7.7.2.5 CAN Boot Mode
      8. 4.7.8  GPIO Assignments
      9. 4.7.9  Secure ROM Function APIs
      10. 4.7.10 Clock Initializations
      11. 4.7.11 Boot Status Information
        1. 4.7.11.1 Booting Status
        2. 4.7.11.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      12. 4.7.12 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
      7. 5.9.7 DCSM Registers to Driverlib Functions
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Examples
        1. 6.11.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        2. 6.11.1.2 Boot Source Code
        3. 6.11.1.3 Erase Source Code
        4. 6.11.1.4 Live DFU Command Functionality
        5. 6.11.1.5 Verify Source Code
        6. 6.11.1.6 SCI Boot Mode Routines
        7. 6.11.1.7 Flash Programming Solution using SCI
    12. 6.12 Flash Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
      4. 6.12.4 FLASH Registers to Driverlib Functions
  9. 7 Dual-Clock Comparator (DCC)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 Block Diagram
    2. 7.2 Module Operation
      1. 7.2.1 Configuring DCC Counters
      2. 7.2.2 Single-Shot Measurement Mode
      3. 7.2.3 Continuous Monitoring Mode
      4. 7.2.4 Error Conditions
    3. 7.3 Interrupts
    4. 7.4 Software
      1. 7.4.1 DCC Examples
        1. 7.4.1.1 DCC Single shot Clock verification
        2. 7.4.1.2 DCC Single shot Clock measurement
        3. 7.4.1.3 DCC Continuous clock monitoring
        4. 7.4.1.4 DCC Continuous clock monitoring
        5. 7.4.1.5 DCC Detection of clock failure
    5. 7.5 DCC Registers
      1. 7.5.1 DCC Base Address Table
      2. 7.5.2 DCC_REGS Registers
      3. 7.5.3 DCC Registers to Driverlib Functions
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital Inputs on ADC Pins (AIOs)
    4. 8.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 8.5  Digital General-Purpose I/O Control
    6. 8.6  Input Qualification
      1. 8.6.1 No Synchronization (Asynchronous Input)
      2. 8.6.2 Synchronization to SYSCLKOUT Only
      3. 8.6.3 Qualification Using a Sampling Window
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Software
      1. 8.9.1 GPIO Examples
        1. 8.9.1.1 Device GPIO Setup
        2. 8.9.1.2 Device GPIO Toggle
        3. 8.9.1.3 Device GPIO Interrupt
        4. 8.9.1.4 External Interrupt (XINT)
      2. 8.9.2 LED Examples
    10. 8.10 GPIO Registers
      1. 8.10.1 GPIO Base Address Table
      2. 8.10.2 GPIO_CTRL_REGS Registers
      3. 8.10.3 GPIO_DATA_REGS Registers
      4. 8.10.4 GPIO_DATA_READ_REGS Registers
      5. 8.10.5 GPIO Registers to Driverlib Functions
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 ePWM and GPIO Output X-BAR
      1. 9.2.1 ePWM X-BAR
        1. 9.2.1.1 ePWM X-BAR Architecture
      2. 9.2.2 GPIO Output X-BAR
        1. 9.2.2.1 GPIO Output X-BAR Architecture
      3. 9.2.3 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 EPWM_XBAR_REGS Registers
      5. 9.3.5 OUTPUT_XBAR_REGS Registers
      6. 9.3.6 Register to Driverlib Function Mapping
        1. 9.3.6.1 INPUTXBAR Registers to Driverlib Functions
        2. 9.3.6.2 XBAR Registers to Driverlib Functions
        3. 9.3.6.3 EPWMXBAR Registers to Driverlib Functions
        4. 9.3.6.4 OUTPUTXBAR Registers to Driverlib Functions
  12. 10Analog Subsystem
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Optimizing Power-Up Time
    3. 10.3 Digital Inputs on ADC Pins (AIOs)
    4. 10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 10.5 Analog Pins and Internal Connections
    6. 10.6 Analog Subsystem Registers
      1. 10.6.1 ASBSYS Base Address Table
      2. 10.6.2 ANALOG_SUBSYS_REGS Registers
  13. 11Analog-to-Digital Converter (ADC)
    1. 11.1  Introduction
      1. 11.1.1 ADC Related Collateral
      2. 11.1.2 Features
      3. 11.1.3 Block Diagram
    2. 11.2  ADC Configurability
      1. 11.2.1 Clock Configuration
      2. 11.2.2 Resolution
      3. 11.2.3 Voltage Reference
        1. 11.2.3.1 External Reference Mode
        2. 11.2.3.2 Internal Reference Mode
        3. 11.2.3.3 Selecting Reference Mode
      4. 11.2.4 Signal Mode
      5. 11.2.5 Expected Conversion Results
      6. 11.2.6 Interpreting Conversion Results
    3. 11.3  SOC Principle of Operation
      1. 11.3.1 SOC Configuration
      2. 11.3.2 Trigger Operation
      3. 11.3.3 ADC Acquisition (Sample and Hold) Window
      4. 11.3.4 ADC Input Models
      5. 11.3.5 Channel Selection
    4. 11.4  SOC Configuration Examples
      1. 11.4.1 Single Conversion from ePWM Trigger
      2. 11.4.2 Oversampled Conversion from ePWM Trigger
      3. 11.4.3 Multiple Conversions from CPU Timer Trigger
      4. 11.4.4 Software Triggering of SOCs
    5. 11.5  ADC Conversion Priority
    6. 11.6  Burst Mode
      1. 11.6.1 Burst Mode Example
      2. 11.6.2 Burst Mode Priority Example
    7. 11.7  EOC and Interrupt Operation
      1. 11.7.1 Interrupt Overflow
      2. 11.7.2 Continue to Interrupt Mode
      3. 11.7.3 Early Interrupt Configuration Mode
    8. 11.8  Post-Processing Blocks
      1. 11.8.1 PPB Offset Correction
      2. 11.8.2 PPB Error Calculation
      3. 11.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 11.8.4 PPB Sample Delay Capture
    9. 11.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 11.9.1 Implementation
      2. 11.9.2 Detecting an Open Input Pin
      3. 11.9.3 Detecting a Shorted Input Pin
    10. 11.10 Power-Up Sequence
    11. 11.11 ADC Calibration
      1. 11.11.1 ADC Zero Offset Calibration
    12. 11.12 ADC Timings
      1. 11.12.1 ADC Timing Diagrams
    13. 11.13 Additional Information
      1. 11.13.1 Ensuring Synchronous Operation
        1. 11.13.1.1 Basic Synchronous Operation
        2. 11.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 11.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 11.13.1.4 Non-overlapping Conversions
      2. 11.13.2 Choosing an Acquisition Window Duration
      3. 11.13.3 Achieving Simultaneous Sampling
      4. 11.13.4 Result Register Mapping
      5. 11.13.5 Internal Temperature Sensor
      6. 11.13.6 Designing an External Reference Circuit
      7. 11.13.7 ADC-DAC Loopback Testing
      8. 11.13.8 Internal Test Mode
      9. 11.13.9 ADC Gain and Offset Calibration
    14. 11.14 Software
      1. 11.14.1 ADC Examples
        1. 11.14.1.1  ADC Software Triggering
        2. 11.14.1.2  ADC ePWM Triggering
        3. 11.14.1.3  ADC Temperature Sensor Conversion
        4. 11.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 11.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 11.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 11.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 11.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 11.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 11.14.1.10 ADC Burst Mode
        11. 11.14.1.11 ADC Burst Mode Oversampling
        12. 11.14.1.12 ADC SOC Oversampling
        13. 11.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
        14. 11.14.1.14 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 11.15 ADC Registers
      1. 11.15.1 ADC Base Address Table
      2. 11.15.2 ADC_RESULT_REGS Registers
      3. 11.15.3 ADC_REGS Registers
      4. 11.15.4 ADC Registers to Driverlib Functions
  14. 12Comparator Subsystem (CMPSS)
    1. 12.1 Introduction
      1. 12.1.1 CMPSS Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 CMPSS Module Variants
      4. 12.1.4 Block Diagram
    2. 12.2 Comparator
    3. 12.3 Reference DAC
    4. 12.4 Ramp Generator
      1. 12.4.1 Ramp Generator Overview
      2. 12.4.2 Ramp Generator Behavior
      3. 12.4.3 Ramp Generator Behavior at Corner Cases
    5. 12.5 Digital Filter
      1. 12.5.1 Filter Initialization Sequence
    6. 12.6 Using the CMPSS
      1. 12.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 12.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 12.6.3 Calibrating the CMPSS
      4. 12.6.4 Enabling and Disabling the CMPSS Clock
    7. 12.7 CMPSS DAC Output
    8. 12.8 Software
      1. 12.8.1 CMPSS Examples
        1. 12.8.1.1 CMPSS Asynchronous Trip
        2. 12.8.1.2 CMPSS Digital Filter Configuration
      2. 12.8.2 CMPSS_LITE Examples
        1. 12.8.2.1 CMPSSLITE Asynchronous Trip
    9. 12.9 CMPSS Registers
      1. 12.9.1 CMPSS Base Address Table
      2. 12.9.2 CMPSS_REGS Registers
      3. 12.9.3 CMPSS_LITE_REGS Registers
      4. 12.9.4 CMPSS Registers to Driverlib Functions
      5. 12.9.5 CMPSS_LITE Registers to Driverlib Functions
  15. 13Enhanced Pulse Width Modulator (ePWM)
    1. 13.1  Introduction
      1. 13.1.1 EPWM Related Collateral
      2. 13.1.2 Submodule Overview
    2. 13.2  Configuring Device Pins
    3. 13.3  ePWM Modules Overview
    4. 13.4  Time-Base (TB) Submodule
      1. 13.4.1 Purpose of the Time-Base Submodule
      2. 13.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 13.4.3 Calculating PWM Period and Frequency
        1. 13.4.3.1 Time-Base Period Shadow Register
        2. 13.4.3.2 Time-Base Clock Synchronization
        3. 13.4.3.3 Time-Base Counter Synchronization
        4. 13.4.3.4 ePWM SYNC Selection
      4. 13.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 13.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 13.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 13.4.7 Global Load
        1. 13.4.7.1 Global Load Pulse Pre-Scalar
        2. 13.4.7.2 One-Shot Load Mode
        3. 13.4.7.3 One-Shot Sync Mode
    5. 13.5  Counter-Compare (CC) Submodule
      1. 13.5.1 Purpose of the Counter-Compare Submodule
      2. 13.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 13.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 13.5.4 Count Mode Timing Waveforms
    6. 13.6  Action-Qualifier (AQ) Submodule
      1. 13.6.1 Purpose of the Action-Qualifier Submodule
      2. 13.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 13.6.3 Action-Qualifier Event Priority
      4. 13.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 13.6.5 Configuration Requirements for Common Waveforms
    7. 13.7  Dead-Band Generator (DB) Submodule
      1. 13.7.1 Purpose of the Dead-Band Submodule
      2. 13.7.2 Dead-band Submodule Additional Operating Modes
      3. 13.7.3 Operational Highlights for the Dead-Band Submodule
    8. 13.8  PWM Chopper (PC) Submodule
      1. 13.8.1 Purpose of the PWM Chopper Submodule
      2. 13.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 13.8.3 Waveforms
        1. 13.8.3.1 One-Shot Pulse
        2. 13.8.3.2 Duty Cycle Control
    9. 13.9  Trip-Zone (TZ) Submodule
      1. 13.9.1 Purpose of the Trip-Zone Submodule
      2. 13.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 13.9.2.1 Trip-Zone Configurations
      3. 13.9.3 Generating Trip Event Interrupts
    10. 13.10 Event-Trigger (ET) Submodule
      1. 13.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 13.11 Digital Compare (DC) Submodule
      1. 13.11.1 Purpose of the Digital Compare Submodule
      2. 13.11.2 Enhanced Trip Action Using CMPSS
      3. 13.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 13.11.4 Operation Highlights of the Digital Compare Submodule
        1. 13.11.4.1 Digital Compare Events
        2. 13.11.4.2 Event Filtering
        3. 13.11.4.3 Valley Switching
    12. 13.12 ePWM Crossbar (X-BAR)
    13. 13.13 Applications to Power Topologies
      1. 13.13.1  Overview of Multiple Modules
      2. 13.13.2  Key Configuration Capabilities
      3. 13.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 13.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 13.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 13.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 13.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 13.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 13.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 13.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 13.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 13.14 Register Lock Protection
    15. 13.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 13.15.1 Operational Description of HRPWM
        1. 13.15.1.1 Controlling the HRPWM Capabilities
        2. 13.15.1.2 HRPWM Source Clock
        3. 13.15.1.3 Configuring the HRPWM
        4. 13.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 13.15.1.5 Principle of Operation
          1. 13.15.1.5.1 Edge Positioning
          2. 13.15.1.5.2 Scaling Considerations
          3. 13.15.1.5.3 Duty Cycle Range Limitation
          4. 13.15.1.5.4 High-Resolution Period
            1. 13.15.1.5.4.1 High-Resolution Period Configuration
        6. 13.15.1.6 Deadband High-Resolution Operation
        7. 13.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 13.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 13.15.1.8.1 #Defines for HRPWM Header Files
          2. 13.15.1.8.2 Implementing a Simple Buck Converter
            1. 13.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 13.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 13.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 13.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 13.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 13.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 13.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 13.15.2.2 Software Usage
          1. 13.15.2.2.1 A Sample of How to Add "Include" Files
          2.        599
          3. 13.15.2.2.2 Declaring an Element
          4.        601
          5. 13.15.2.2.3 Initializing With a Scale Factor Value
          6.        603
          7. 13.15.2.2.4 SFO Function Calls
    16. 13.16 Software
      1. 13.16.1 EPWM Examples
        1. 13.16.1.1  ePWM Trip Zone
        2. 13.16.1.2  ePWM Up Down Count Action Qualifier
        3. 13.16.1.3  ePWM Synchronization
        4. 13.16.1.4  ePWM Digital Compare
        5. 13.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 13.16.1.6  ePWM Valley Switching
        7. 13.16.1.7  ePWM Digital Compare Edge Filter
        8. 13.16.1.8  ePWM Deadband
        9. 13.16.1.9  ePWM Chopper
        10. 13.16.1.10 EPWM Configure Signal
        11. 13.16.1.11 Realization of Monoshot mode
        12. 13.16.1.12 EPWM Action Qualifier (epwm_up_aq)
      2. 13.16.2 HRPWM Examples
        1. 13.16.2.1 HRPWM Duty Control with SFO
        2. 13.16.2.2 HRPWM Slider
        3. 13.16.2.3 HRPWM Period Control
        4. 13.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 13.16.2.5 HRPWM Slider Test
        6. 13.16.2.6 HRPWM Duty Up Count
        7. 13.16.2.7 HRPWM Period Up-Down Count
    17. 13.17 ePWM Registers
      1. 13.17.1 EPWM Base Address Table
      2. 13.17.2 EPWM_REGS Registers
      3. 13.17.3 Register to Driverlib Function Mapping
        1. 13.17.3.1 EPWM Registers to Driverlib Functions
        2. 13.17.3.2 HRPWM Registers to Driverlib Functions
  16. 14Enhanced Capture (eCAP)
    1. 14.1 Introduction
      1. 14.1.1 Features
      2. 14.1.2 ECAP Related Collateral
    2. 14.2 Description
    3. 14.3 Configuring Device Pins for the eCAP
    4. 14.4 Capture and APWM Operating Mode
    5. 14.5 Capture Mode Description
      1. 14.5.1 Event Prescaler
      2. 14.5.2 Edge Polarity Select and Qualifier
      3. 14.5.3 Continuous/One-Shot Control
      4. 14.5.4 32-Bit Counter and Phase Control
      5. 14.5.5 CAP1-CAP4 Registers
      6. 14.5.6 eCAP Synchronization
        1. 14.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 14.5.7 Interrupt Control
      8. 14.5.8 Shadow Load and Lockout Control
      9. 14.5.9 APWM Mode Operation
    6. 14.6 Application of the eCAP Module
      1. 14.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 14.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 14.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 14.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 14.7 Application of the APWM Mode
      1. 14.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 14.8 Software
      1. 14.8.1 ECAP Examples
        1. 14.8.1.1 eCAP APWM Example
        2. 14.8.1.2 eCAP Capture PWM Example
        3. 14.8.1.3 eCAP APWM Phase-shift Example
    9. 14.9 eCAP Registers
      1. 14.9.1 ECAP Base Address Table
      2. 14.9.2 ECAP_REGS Registers
      3. 14.9.3 ECAP Registers to Driverlib Functions
  17. 15Enhanced Quadrature Encoder Pulse (eQEP)
    1. 15.1  Introduction
      1. 15.1.1 EQEP Related Collateral
    2. 15.2  Configuring Device Pins
    3. 15.3  Description
      1. 15.3.1 EQEP Inputs
      2. 15.3.2 Functional Description
      3. 15.3.3 eQEP Memory Map
    4. 15.4  Quadrature Decoder Unit (QDU)
      1. 15.4.1 Position Counter Input Modes
        1. 15.4.1.1 Quadrature Count Mode
        2. 15.4.1.2 Direction-Count Mode
        3. 15.4.1.3 Up-Count Mode
        4. 15.4.1.4 Down-Count Mode
      2. 15.4.2 eQEP Input Polarity Selection
      3. 15.4.3 Position-Compare Sync Output
    5. 15.5  Position Counter and Control Unit (PCCU)
      1. 15.5.1 Position Counter Operating Modes
        1. 15.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 15.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 15.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 15.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 15.5.2 Position Counter Latch
        1. 15.5.2.1 Index Event Latch
        2. 15.5.2.2 Strobe Event Latch
      3. 15.5.3 Position Counter Initialization
      4. 15.5.4 eQEP Position-compare Unit
    6. 15.6  eQEP Edge Capture Unit
    7. 15.7  eQEP Watchdog
    8. 15.8  eQEP Unit Timer Base
    9. 15.9  QMA Module
      1. 15.9.1 Modes of Operation
        1. 15.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 15.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 15.9.2 Interrupt and Error Generation
    10. 15.10 eQEP Interrupt Structure
    11. 15.11 Software
      1. 15.11.1 EQEP Examples
        1. 15.11.1.1 Frequency Measurement Using eQEP
        2. 15.11.1.2 Position and Speed Measurement Using eQEP
        3. 15.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 15.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 15.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 15.12 eQEP Registers
      1. 15.12.1 EQEP Base Address Table
      2. 15.12.2 EQEP_REGS Registers
      3. 15.12.3 EQEP Registers to Driverlib Functions
  18. 16Controller Area Network (CAN)
    1. 16.1  Introduction
      1. 16.1.1 DCAN Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
        1. 16.1.3.1 CAN Core
        2. 16.1.3.2 Message Handler
        3. 16.1.3.3 Message RAM
        4. 16.1.3.4 Registers and Message Object Access (IFx)
    2. 16.2  Functional Description
      1. 16.2.1 Configuring Device Pins
      2. 16.2.2 Address/Data Bus Bridge
    3. 16.3  Operating Modes
      1. 16.3.1 Initialization
      2. 16.3.2 CAN Message Transfer (Normal Operation)
        1. 16.3.2.1 Disabled Automatic Retransmission
        2. 16.3.2.2 Auto-Bus-On
      3. 16.3.3 Test Modes
        1. 16.3.3.1 Silent Mode
        2. 16.3.3.2 Loopback Mode
        3. 16.3.3.3 External Loopback Mode
        4. 16.3.3.4 Loopback Combined with Silent Mode
    4. 16.4  Multiple Clock Source
    5. 16.5  Interrupt Functionality
      1. 16.5.1 Message Object Interrupts
      2. 16.5.2 Status Change Interrupts
      3. 16.5.3 Error Interrupts
      4. 16.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 16.5.5 Interrupt Topologies
    6. 16.6  Parity Check Mechanism
      1. 16.6.1 Behavior on Parity Error
    7. 16.7  Debug Mode
    8. 16.8  Module Initialization
    9. 16.9  Configuration of Message Objects
      1. 16.9.1 Configuration of a Transmit Object for Data Frames
      2. 16.9.2 Configuration of a Transmit Object for Remote Frames
      3. 16.9.3 Configuration of a Single Receive Object for Data Frames
      4. 16.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 16.9.5 Configuration of a FIFO Buffer
    10. 16.10 Message Handling
      1. 16.10.1  Message Handler Overview
      2. 16.10.2  Receive/Transmit Priority
      3. 16.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 16.10.4  Updating a Transmit Object
      5. 16.10.5  Changing a Transmit Object
      6. 16.10.6  Acceptance Filtering of Received Messages
      7. 16.10.7  Reception of Data Frames
      8. 16.10.8  Reception of Remote Frames
      9. 16.10.9  Reading Received Messages
      10. 16.10.10 Requesting New Data for a Receive Object
      11. 16.10.11 Storing Received Messages in FIFO Buffers
      12. 16.10.12 Reading from a FIFO Buffer
    11. 16.11 CAN Bit Timing
      1. 16.11.1 Bit Time and Bit Rate
        1. 16.11.1.1 Synchronization Segment
        2. 16.11.1.2 Propagation Time Segment
        3. 16.11.1.3 Phase Buffer Segments and Synchronization
        4. 16.11.1.4 Oscillator Tolerance Range
      2. 16.11.2 Configuration of the CAN Bit Timing
        1. 16.11.2.1 Calculation of the Bit Timing Parameters
        2. 16.11.2.2 Example for Bit Timing at High Baudrate
        3. 16.11.2.3 Example for Bit Timing at Low Baudrate
    12. 16.12 Message Interface Register Sets
      1. 16.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 16.12.2 Message Interface Register Set 3 (IF3)
    13. 16.13 Message RAM
      1. 16.13.1 Structure of Message Objects
      2. 16.13.2 Addressing Message Objects in RAM
      3. 16.13.3 Message RAM Representation in Debug Mode
    14. 16.14 Software
      1. 16.14.1 CAN Examples
        1. 16.14.1.1 CAN External Loopback
        2. 16.14.1.2 CAN External Loopback with Interrupts
        3. 16.14.1.3 CAN Transmit and Receive Configurations
        4. 16.14.1.4 CAN Error Generation Example
        5. 16.14.1.5 CAN Remote Request Loopback
        6. 16.14.1.6 CAN example that illustrates the usage of Mask registers
    15. 16.15 CAN Registers
      1. 16.15.1 CAN Base Address Table
      2. 16.15.2 CAN_REGS Registers
      3. 16.15.3 CAN Registers to Driverlib Functions
  19. 17Inter-Integrated Circuit Module (I2C)
    1. 17.1 Introduction
      1. 17.1.1 I2C Related Collateral
      2. 17.1.2 Features
      3. 17.1.3 Features Not Supported
      4. 17.1.4 Functional Overview
      5. 17.1.5 Clock Generation
      6. 17.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 17.1.6.1 Formula for the Master Clock Period
    2. 17.2 Configuring Device Pins
    3. 17.3 I2C Module Operational Details
      1. 17.3.1  Input and Output Voltage Levels
      2. 17.3.2  Selecting Pullup Resistors
      3. 17.3.3  Data Validity
      4. 17.3.4  Operating Modes
      5. 17.3.5  I2C Module START and STOP Conditions
      6. 17.3.6  Non-repeat Mode versus Repeat Mode
      7. 17.3.7  Serial Data Formats
        1. 17.3.7.1 7-Bit Addressing Format
        2. 17.3.7.2 10-Bit Addressing Format
        3. 17.3.7.3 Free Data Format
        4. 17.3.7.4 Using a Repeated START Condition
      8. 17.3.8  Clock Synchronization
      9. 17.3.9  Arbitration
      10. 17.3.10 Digital Loopback Mode
      11. 17.3.11 NACK Bit Generation
    4. 17.4 Interrupt Requests Generated by the I2C Module
      1. 17.4.1 Basic I2C Interrupt Requests
      2. 17.4.2 I2C FIFO Interrupts
    5. 17.5 Resetting or Disabling the I2C Module
    6. 17.6 Software
      1. 17.6.1 I2C Examples
        1. 17.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 17.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 17.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 17.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 17.6.1.5 I2C EEPROM
        6. 17.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 17.6.1.7 I2C EEPROM
        8. 17.6.1.8 I2C controller target communication using FIFO interrupts
        9. 17.6.1.9 I2C EEPROM
    7. 17.7 I2C Registers
      1. 17.7.1 I2C Base Address Table
      2. 17.7.2 I2C_REGS Registers
      3. 17.7.3 I2C Registers to Driverlib Functions
  20. 18Serial Communications Interface (SCI)
    1. 18.1  Introduction
      1. 18.1.1 Features
      2. 18.1.2 SCI Related Collateral
      3. 18.1.3 Block Diagram
    2. 18.2  Architecture
    3. 18.3  SCI Module Signal Summary
    4. 18.4  Configuring Device Pins
    5. 18.5  Multiprocessor and Asynchronous Communication Modes
    6. 18.6  SCI Programmable Data Format
    7. 18.7  SCI Multiprocessor Communication
      1. 18.7.1 Recognizing the Address Byte
      2. 18.7.2 Controlling the SCI TX and RX Features
      3. 18.7.3 Receipt Sequence
    8. 18.8  Idle-Line Multiprocessor Mode
      1. 18.8.1 Idle-Line Mode Steps
      2. 18.8.2 Block Start Signal
      3. 18.8.3 Wake-Up Temporary (WUT) Flag
        1. 18.8.3.1 Sending a Block Start Signal
      4. 18.8.4 Receiver Operation
    9. 18.9  Address-Bit Multiprocessor Mode
      1. 18.9.1 Sending an Address
    10. 18.10 SCI Communication Format
      1. 18.10.1 Receiver Signals in Communication Modes
      2. 18.10.2 Transmitter Signals in Communication Modes
    11. 18.11 SCI Port Interrupts
      1. 18.11.1 Break Detect
    12. 18.12 SCI Baud Rate Calculations
    13. 18.13 SCI Enhanced Features
      1. 18.13.1 SCI FIFO Description
      2. 18.13.2 SCI Auto-Baud
      3. 18.13.3 Autobaud-Detect Sequence
    14. 18.14 Software
      1. 18.14.1 SCI Examples
        1. 18.14.1.1 Tune Baud Rate via UART Example
        2. 18.14.1.2 SCI FIFO Digital Loop Back
        3. 18.14.1.3 SCI Digital Loop Back with Interrupts
        4. 18.14.1.4 SCI Echoback
        5. 18.14.1.5 stdout redirect example
    15. 18.15 SCI Registers
      1. 18.15.1 SCI Base Address Table
      2. 18.15.2 SCI_REGS Registers
      3. 18.15.3 SCI Registers to Driverlib Functions
  21. 19Serial Peripheral Interface (SPI)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 SPI Related Collateral
      3. 19.1.3 Block Diagram
    2. 19.2 System-Level Integration
      1. 19.2.1 SPI Module Signals
      2. 19.2.2 Configuring Device Pins
        1. 19.2.2.1 GPIOs Required for High-Speed Mode
      3. 19.2.3 SPI Interrupts
    3. 19.3 SPI Operation
      1. 19.3.1 Introduction to Operation
      2. 19.3.2 Master Mode
      3. 19.3.3 Slave Mode
      4. 19.3.4 Data Format
        1. 19.3.4.1 Transmission of Bit from SPIRXBUF
      5. 19.3.5 Baud Rate Selection
        1. 19.3.5.1 Baud Rate Determination
        2. 19.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 19.3.6 SPI Clocking Schemes
      7. 19.3.7 SPI FIFO Description
      8. 19.3.8 SPI High-Speed Mode
      9. 19.3.9 SPI 3-Wire Mode Description
    4. 19.4 Programming Procedure
      1. 19.4.1 Initialization Upon Reset
      2. 19.4.2 Configuring the SPI
      3. 19.4.3 Configuring the SPI for High-Speed Mode
      4. 19.4.4 Data Transfer Example
      5. 19.4.5 SPI 3-Wire Mode Code Examples
        1. 19.4.5.1 3-Wire Master Mode Transmit
        2.       913
          1. 19.4.5.2.1 3-Wire Master Mode Receive
        3.       915
          1. 19.4.5.2.1 3-Wire Slave Mode Transmit
        4.       917
          1. 19.4.5.2.1 3-Wire Slave Mode Receive
      6. 19.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 19.5 Software
      1. 19.5.1 SPI Examples
        1. 19.5.1.1 SPI Digital Loopback
        2. 19.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 19.5.1.3 SPI EEPROM
    6. 19.6 SPI Registers
      1. 19.6.1 SPI Base Address Table
      2. 19.6.2 SPI_REGS Registers
      3. 19.6.3 SPI Registers to Driverlib Functions
  22. 20Embedded Pattern Generator (EPG)
    1. 20.1 Introduction
      1. 20.1.1 Features
      2. 20.1.2 EPG Block Diagram
      3. 20.1.3 EPG Related Collateral
    2. 20.2 Clock Generator Modules
      1. 20.2.1 DCLK (50% duty cycle clock)
      2. 20.2.2 Clock Stop
    3. 20.3 Signal Generator Module
    4. 20.4 EPG Peripheral Signal Mux Selection
    5. 20.5 EPG Example Use Cases
      1. 20.5.1 EPG Example: Synchronous Clocks with Offset
        1. 20.5.1.1 Synchronous Clocks with Offset Register Configuration
      2. 20.5.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 20.5.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 20.5.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 20.5.3.1 Serial Data Bit Stream (MSB first) Register Configuration
    6. 20.6 EPG Interrupt
    7. 20.7 Software
      1. 20.7.1 EPG Examples
        1. 20.7.1.1 EPG Generating Synchronous Clocks
        2. 20.7.1.2 EPG Generating Two Offset Clocks
        3. 20.7.1.3 EPG Generating Two Offset Clocks With SIGGEN
        4. 20.7.1.4 EPG Generate Serial Data
        5. 20.7.1.5 EPG Generate Serial Data Shift Mode
    8. 20.8 EPG Registers
      1. 20.8.1 EPG Base Address Table
      2. 20.8.2 EPG_REGS Registers
      3. 20.8.3 EPG_MUX_REGS Registers
      4. 20.8.4 EPG Registers to Driverlib Functions
  23. 21Revision History

20.8.2 EPG_REGS Registers

Table 20-6 lists the memory-mapped registers for the EPG_REGS registers. All register offset addresses not listed in Table 20-6 should be considered as reserved locations and the register contents should not be modified.

Table 20-6 EPG_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hGCTL0EPG Global control register 0Go
2hGCTL1EPG Global control register 1Go
4hGCTL2EPG Global control register 2Go
6hGCTL3EPG Global control register 3Go
8hEPGLOCKEPG LOCK RegisterGo
AhEPGCOMMITEPG COMMIT registerGo
ChGINTSTSEPG Global interrupt status register.Go
EhGINTENEPG Global interrupt enable register.Go
10hGINTCLREPG Global interrupt clear register.Go
12hGINTFRCEPG Global interrupt force register.Go
18hCLKDIV0_CTL0Clock divider 0's control register 0Go
1EhCLKDIV0_CLKOFFSETClock divider 0's clock offset valueGo
24hCLKDIV1_CTL0Clock divider 1's control register 0Go
2AhCLKDIV1_CLKOFFSETClock divider 1's clock offset valueGo
30hSIGGEN0_CTL0Signal generator 0's control register 0Go
32hSIGGEN0_CTL1Signal generator 0's control register 1Go
38hSIGGEN0_DATA0Signal generator 0's data register 0Go
3AhSIGGEN0_DATA1Signal generator 0's data register 1Go
3ChSIGGEN0_DATA0_ACTIVESignal generator 0's data active register 0Go
3EhSIGGEN0_DATA1_ACTIVESignal generator 0's data active register 1Go

Complex bit access types are encoded to fit into small table cells. Table 20-7 shows the codes that are used for access types in this section.

Table 20-7 EPG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

20.8.2.1 GCTL0 Register (Offset = 0h) [Reset = 00000000h]

GCTL0 is shown in Figure 20-8 and described in Table 20-8.

Return to the Summary Table.

EPG Global control register 0

Figure 20-8 GCTL0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
EPGOUT7SELEPGOUT6SELEPGOUT5SELEPGOUT4SELEPGOUT3SELEPGOUT2SELEPGOUT1SELEPGOUT0SEL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDEN
R-0hR/W-0h
Table 20-8 GCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15EPGOUT7SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

14EPGOUT6SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

13EPGOUT5SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

12EPGOUT4SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

11EPGOUT3SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

10EPGOUT2SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

9EPGOUT1SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

8EPGOUT0SELR/W0h0 : Selects signal mux output
1 : Selects clock mux output

Reset type: SYSRSn

7-1RESERVEDR0hReserved
0ENR/W0h0 : EPG module is disabled
1 : EPG module is enabled, clock generators and signal generators are functional.

Reset type: SYSRSn

20.8.2.2 GCTL1 Register (Offset = 2h) [Reset = 00000000h]

GCTL1 is shown in Figure 20-9 and described in Table 20-9.

Return to the Summary Table.

EPG Global control register 1

Figure 20-9 GCTL1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDSIGGEN0_CLKSEL
R/W-0hR/W-0hR/W-0hR/W-0h
Table 20-9 GCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RESERVEDR/W0hReserved
6-4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2-0SIGGEN0_CLKSELR/W0hClock source select of SIGGEN0:
0x0 : CLKGEN0.CLKOUT0_GCLK
0x1 : CLKGEN0.CLKOUT1_GCLK
0x2 : CLKGEN0.CLKOUT2_GCLK
0x3 : CLKGEN0.CLKOUT3_GCLK
0x4 : CLKGEN1.CLKOUT0_GCLK
0x5 : CLKGEN1.CLKOUT1_GCLK
0x6 : CLKGEN1.CLKOUT2_GCLK
0x7 : CLKGEN1.CLKOUT3_GCLK

Reset type: SYSRSn

20.8.2.3 GCTL2 Register (Offset = 4h) [Reset = 00000000h]

GCTL2 is shown in Figure 20-10 and described in Table 20-10.

Return to the Summary Table.

EPG Global control register 2

Figure 20-10 GCTL2 Register
3130292827262524
RESERVEDEPGOUT7_CLKOUTSELRESERVEDEPGOUT6_CLKOUTSEL
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDEPGOUT5_CLKOUTSELRESERVEDEPGOUT4_CLKOUTSEL
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDEPGOUT3_CLKOUTSELRESERVEDEPGOUT2_CLKOUTSEL
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDEPGOUT1_CLKOUTSELRESERVEDEPGOUT0_CLKOUTSEL
R/W-0hR/W-0hR/W-0hR/W-0h
Table 20-10 GCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30-28EPGOUT7_CLKOUTSELR/W0hOutput 7 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

27RESERVEDR/W0hReserved
26-24EPGOUT6_CLKOUTSELR/W0hOutput 6 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

23RESERVEDR/W0hReserved
22-20EPGOUT5_CLKOUTSELR/W0hOutput 5 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

19RESERVEDR/W0hReserved
18-16EPGOUT4_CLKOUTSELR/W0hOutput 4 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

15RESERVEDR/W0hReserved
14-12EPGOUT3_CLKOUTSELR/W0hOutput 3 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

11RESERVEDR/W0hReserved
10-8EPGOUT2_CLKOUTSELR/W0hOutput 2 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

7RESERVEDR/W0hReserved
6-4EPGOUT1_CLKOUTSELR/W0hOutput 1 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

3RESERVEDR/W0hReserved
2-0EPGOUT0_CLKOUTSELR/W0hOutput 0 signal source select:
0x0 : CLKGEN0.CLKOUT0_DCLK
0x1 : CLKGEN0.CLKOUT1_DCLK
0x2 : CLKGEN0.CLKOUT2_DCLK
0x3 : CLKGEN0.CLKOUT3_DCLK
0x4 : CLKGEN1.CLKOUT0_DCLK
0x5 : CLKGEN1.CLKOUT1_DCLK
0x6 : CLKGEN1.CLKOUT2_DCLK
0x7 : CLKGEN1.CLKOUT3_DCLK

Reset type: SYSRSn

20.8.2.4 GCTL3 Register (Offset = 6h) [Reset = 00000000h]

GCTL3 is shown in Figure 20-11 and described in Table 20-11.

Return to the Summary Table.

EPG Global control register 3

Figure 20-11 GCTL3 Register
3130292827262524
EPGOUT7_SIGOUTSELEPGOUT6_SIGOUTSEL
R/W-0hR/W-0h
2322212019181716
EPGOUT5_SIGOUTSELEPGOUT4_SIGOUTSEL
R/W-0hR/W-0h
15141312111098
EPGOUT3_SIGOUTSELEPGOUT2_SIGOUTSEL
R/W-0hR/W-0h
76543210
EPGOUT1_SIGOUTSELEPGOUT0_SIGOUTSEL
R/W-0hR/W-0h
Table 20-11 GCTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28EPGOUT7_SIGOUTSELR/W0hOutput 7 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

27-24EPGOUT6_SIGOUTSELR/W0hOutput 6 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

23-20EPGOUT5_SIGOUTSELR/W0hOutput 5 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

19-16EPGOUT4_SIGOUTSELR/W0hOutput 4 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

15-12EPGOUT3_SIGOUTSELR/W0hOutput 3 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

11-8EPGOUT2_SIGOUTSELR/W0hOutput 2 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

7-4EPGOUT1_SIGOUTSELR/W0hOutput 1 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

3-0EPGOUT0_SIGOUTSELR/W0hOutput 0 source select:
0x0 : SIGGEN0.DATATRANOUT0
0x1 : SIGGEN0.DATATRANOUT1
0x2 : SIGGEN0.DATATRANOUT2
0x3 : SIGGEN0.DATATRANOUT3
0x4 : SIGGEN0.DATATRANOUT4
0x5 : SIGGEN0.DATATRANOUT5
0x6 : SIGGEN0.DATATRANOUT6
0x7 : SIGGEN0.DATATRANOUT7
0x8 : SIGGEN1.DATATRANOUT0
0x9 : SIGGEN1.DATATRANOUT1
0xA : SIGGEN1.DATATRANOUT2
0xB : SIGGEN1.DATATRANOUT3
0xC : SIGGEN1.DATATRANOUT4
0xD : SIGGEN1.DATATRANOUT5
0xE : SIGGEN1.DATATRANOUT6
0xF : SIGGEN1.DATATRANOUT7

Reset type: SYSRSn

20.8.2.5 EPGLOCK Register (Offset = 8h) [Reset = 00000000h]

EPGLOCK is shown in Figure 20-12 and described in Table 20-12.

Return to the Summary Table.

EPG LOCK Register

Figure 20-12 EPGLOCK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
76543210
SIGGEN0_CTL1SIGGEN0_CTL0CLKDIV1_CTL0CLKDIV0_CTL0GCTL3GCTL2GCTL1GCTL0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-12 EPGLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7SIGGEN0_CTL1R/W0h0: Writes to SIGGEN0_CTL1 register is allowed.
1: Writes to SIGGEN0_CTL1 register is not allowed.

Reset type: SYSRSn

6SIGGEN0_CTL0R/W0h0: Writes to SIGGEN0_CTL0 register is allowed.
1: Writes to SIGGEN0_CTL0 register is not allowed.

Reset type: SYSRSn

5CLKDIV1_CTL0R/W0h0: Writes to CLKDIV1_CTL0 register is allowed.
1: Writes to CLKDIV1_CTL0 register is not allowed.

Reset type: SYSRSn

4CLKDIV0_CTL0R/W0h0: Writes to CLKDIV0_CTL0 register is allowed.
1: Writes to CLKDIV0_CTL0 register is not allowed.

Reset type: SYSRSn

3GCTL3R/W0h0: Writes to GCTL3 register is allowed.
1: Writes to GCTL3 register is not allowed.

Reset type: SYSRSn

2GCTL2R/W0h0: Writes to GCTL2 register is allowed.
1: Writes to GCTL2 register is not allowed.

Reset type: SYSRSn

1GCTL1R/W0h0: Writes to GCTL1 register is allowed.
1: Writes to GCTL1 register is not allowed.

Reset type: SYSRSn

0GCTL0R/W0h0: Writes to GCTL0 register is allowed.
1: Writes to GCTL0 register is not allowed.

Reset type: SYSRSn

20.8.2.6 EPGCOMMIT Register (Offset = Ah) [Reset = 00000000h]

EPGCOMMIT is shown in Figure 20-13 and described in Table 20-13.

Return to the Summary Table.

EPG COMMIT register

Figure 20-13 EPGCOMMIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVED
R-0hR/WSonce-0hR/WSonce-0h
76543210
SIGGEN0_CTL1SIGGEN0_CTL0CLKDIV1_CTL0CLKDIV0_CTL0GCTL3GCTL2GCTL1GCTL0
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 20-13 EPGCOMMIT Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9RESERVEDR/WSonce0hReserved
8RESERVEDR/WSonce0hReserved
7SIGGEN0_CTL1R/WSonce0h0: Writes to EPGLOCK.SIGGEN0_CTL1 field is allowed.
1: Writes to EPGLOCK.SIGGEN0_CTL1 field is not allowed.

Reset type: SYSRSn

6SIGGEN0_CTL0R/WSonce0h0: Writes to EPGLOCK.SIGGEN0_CTL0 field is allowed.
1: Writes to EPGLOCK.SIGGEN0_CTL0 field is not allowed.

Reset type: SYSRSn

5CLKDIV1_CTL0R/WSonce0h0: Writes to EPGLOCK.CLKDIV1_CTL0 field is allowed.
1: Writes to EPGLOCK.CLKDIV1_CTL0 field is not allowed.

Reset type: SYSRSn

4CLKDIV0_CTL0R/WSonce0h0: Writes to EPGLOCK.CLKDIV0_CTL0 field is allowed.
1: Writes to EPGLOCK.CLKDIV0_CTL0 field is not allowed.

Reset type: SYSRSn

3GCTL3R/WSonce0h0: Writes to EPGLOCK.GCTL3 field is allowed.
1: Writes to EPGLOCK.GCTL3 field is not allowed.

Reset type: SYSRSn

2GCTL2R/WSonce0h0: Writes to EPGLOCK.GCTL2 field is allowed.
1: Writes to EPGLOCK.GCTL2 field is not allowed.

Reset type: SYSRSn

1GCTL1R/WSonce0h0: Writes to EPGLOCK.GCTL1 field is allowed.
1: Writes to EPGLOCK.GCTL1 field is not allowed.

Reset type: SYSRSn

0GCTL0R/WSonce0h0: Writes to EPGLOCK.GCTL0 field is allowed.
1: Writes to EPGLOCK.GCTL0 field is not allowed.

Reset type: SYSRSn

20.8.2.7 GINTSTS Register (Offset = Ch) [Reset = 00000000h]

GINTSTS is shown in Figure 20-14 and described in Table 20-14.

Return to the Summary Table.

EPG Global interrupt status register.

Figure 20-14 GINTSTS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDSIGGEN0_FILLSIGGEN0_DONEINT
R-0hR-0hR-0hR-0hR-0hR-0h
Table 20-14 GINTSTS Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4RESERVEDR0hReserved
3RESERVEDR0hReserved
2SIGGEN0_FILLR0h0: Do not fill data in SIGGEN0
1: Fill data in SIGGEN0

This status bit does not get set in BIT_BANG mode. In all other modes, the SIGGEN0_FILL bit is set high after the signal generator has completed BITLENGTH/2 shifts.

Note: For odd values of BITLENGTH, BITLENGTH/2 is rounded down to the nearest integer.

Reset type: SYSRSn

1SIGGEN0_DONER0h0: Operation of SIGGEN0 is in progress
1: Operation of SIGGEN0 has completed

This status bit does not get set in BIT_BANG mode. In all other modes, the SIGGEN0_DONE bit is set high after the signal generator has completed BITLENGTH shifts.

Reset type: SYSRSn

0INTR0hGlobal interrupt flag. This bit is set when an interrupt is fired, and cleared by writing 1 to GINTCLR.INT. While the INT status bit is set, new EPG interrupts cannot be generated until the bit has been cleared.

Reset type: SYSRSn

20.8.2.8 GINTEN Register (Offset = Eh) [Reset = 00000000h]

GINTEN is shown in Figure 20-15 and described in Table 20-15.

Return to the Summary Table.

EPG Global interrupt enable register.

Figure 20-15 GINTEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDSIGGEN0_FILLSIGGEN0_DONERESERVED
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 20-15 GINTEN Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2SIGGEN0_FILLR/W0h0: Disable interrupt generation when SIGGEN0_FILL bits is set.
1: Enable interrupt generation when SIGGEN0_FILL bits is set.

Reset type: SYSRSn

1SIGGEN0_DONER/W0h0: Disable interrupt generation when SIGGEN0_DONE bits is set.
1: Enable interrupt generation when SIGGEN0_DONE bits is set.

Reset type: SYSRSn

0RESERVEDR0hReserved

20.8.2.9 GINTCLR Register (Offset = 10h) [Reset = 00000000h]

GINTCLR is shown in Figure 20-16 and described in Table 20-16.

Return to the Summary Table.

EPG Global interrupt clear register.

Figure 20-16 GINTCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDSIGGEN0_FILLSIGGEN0_DONEINT
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 20-16 GINTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4RESERVEDR-0/W1C0hReserved
3RESERVEDR-0/W1C0hReserved
2SIGGEN0_FILLR-0/W1C0h0: No effect
1: Clear SIGGEN0_FILL flag bit.

Reset type: SYSRSn

1SIGGEN0_DONER-0/W1C0h0: No effect
1: Clear SIGGEN0_DONE flag bit.

Reset type: SYSRSn

0INTR-0/W1C0h0: No effect
1: Clear INT flag bit.

Reset type: SYSRSn

20.8.2.10 GINTFRC Register (Offset = 12h) [Reset = 00000000h]

GINTFRC is shown in Figure 20-17 and described in Table 20-17.

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EPG Global interrupt force register.

Figure 20-17 GINTFRC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDSIGGEN0_FILLSIGGEN0_DONERESERVED
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0h
Table 20-17 GINTFRC Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4RESERVEDR-0/W1S0hReserved
3RESERVEDR-0/W1S0hReserved
2SIGGEN0_FILLR-0/W1S0h0: No effect
1: set SIGGEN0_FILL flag bit.

Reset type: SYSRSn

1SIGGEN0_DONER-0/W1S0h0: No effect
1: set SIGGEN0_DONE flag bit.

Reset type: SYSRSn

0RESERVEDR0hReserved

20.8.2.11 CLKDIV0_CTL0 Register (Offset = 18h) [Reset = 00000000h]

CLKDIV0_CTL0 is shown in Figure 20-18 and described in Table 20-18.

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Clock divider 0's control register 0

Figure 20-18 CLKDIV0_CTL0 Register
31302928272625242322212019181716
RESERVEDCLKSTOP
R-0hR/W-0h
1514131211109876543210
RESERVEDPRD
R-0hR/W-0h
Table 20-18 CLKDIV0_CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16CLKSTOPR/W0hDetermines on which of the CLKOUTs edge clock generation is stopped following a clear of SIGGEN0_CTL0.EN.
000 : Stop on CLKOUT0
010 : Stop on CLKOUT1
100 : Stop on CLKOUT2
110 : Stop on CLKOUT3

Reset type: SYSRSn

15-8RESERVEDR0hReserved
7-0PRDR/W0hClock divider period: Clock divider counter counts up to period (PRD) and snaps back to 0.

Reset type: SYSRSn

20.8.2.12 CLKDIV0_CLKOFFSET Register (Offset = 1Eh) [Reset = 00000000h]

CLKDIV0_CLKOFFSET is shown in Figure 20-19 and described in Table 20-19.

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Clock divider 0's clock offset value

Figure 20-19 CLKDIV0_CLKOFFSET Register
31302928272625242322212019181716
CLK3OFFSETCLK2OFFSET
R/W-0hR/W-0h
1514131211109876543210
CLK1OFFSETCLK0OFFSET
R/W-0hR/W-0h
Table 20-19 CLKDIV0_CLKOFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-24CLK3OFFSETR/W0hNumber of source clock cycles by which the divided clock output 3 (CLKOUT3) is delayed.

Reset type: SYSRSn

23-16CLK2OFFSETR/W0hNumber of source clock cycles by which the divided clock output 2 (CLKOUT2) is delayed.

Reset type: SYSRSn

15-8CLK1OFFSETR/W0hNumber of source clock cycles by which the divided clock output 1 (CLKOUT1) is delayed.

Reset type: SYSRSn

7-0CLK0OFFSETR/W0hNumber of source clock cycles by which the divided clock output 0 (CLKOUT0) is delayed.

Reset type: SYSRSn

20.8.2.13 CLKDIV1_CTL0 Register (Offset = 24h) [Reset = 00000000h]

CLKDIV1_CTL0 is shown in Figure 20-20 and described in Table 20-20.

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Clock divider 1's control register 0

Figure 20-20 CLKDIV1_CTL0 Register
31302928272625242322212019181716
RESERVEDCLKSTOP
R-0hR/W-0h
1514131211109876543210
RESERVEDPRD
R-0hR/W-0h
Table 20-20 CLKDIV1_CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16CLKSTOPR/W0hDetermines on which of the CLKOUTs edge clock generation is stopped following a clear of SIGGEN1_CTL0.EN.
000 : Stop on CLKOUT0
010 : Stop on CLKOUT1
100 : Stop on CLKOUT2
110 : Stop on CLKOUT3

Reset type: SYSRSn

15-8RESERVEDR0hReserved
7-0PRDR/W0hClock divider period: Clock divider counter counts up to period (PRD) and snaps back to 0.

Reset type: SYSRSn

20.8.2.14 CLKDIV1_CLKOFFSET Register (Offset = 2Ah) [Reset = 00000000h]

CLKDIV1_CLKOFFSET is shown in Figure 20-21 and described in Table 20-21.

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Clock divider 1's clock offset value

Figure 20-21 CLKDIV1_CLKOFFSET Register
31302928272625242322212019181716
CLK3OFFSETCLK2OFFSET
R/W-0hR/W-0h
1514131211109876543210
CLK1OFFSETCLK0OFFSET
R/W-0hR/W-0h
Table 20-21 CLKDIV1_CLKOFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-24CLK3OFFSETR/W0hNumber of source clock cycles by which the divided clock output 3 (CLKOUT3) is delayed.

Reset type: SYSRSn

23-16CLK2OFFSETR/W0hNumber of source clock cycles by which the divided clock output 2 (CLKOUT2) is delayed.

Reset type: SYSRSn

15-8CLK1OFFSETR/W0hNumber of source clock cycles by which the divided clock output 1 (CLKOUT1) is delayed.

Reset type: SYSRSn

7-0CLK0OFFSETR/W0hNumber of source clock cycles by which the divided clock output 0 (CLKOUT0) is delayed.

Reset type: SYSRSn

20.8.2.15 SIGGEN0_CTL0 Register (Offset = 30h) [Reset = 00000000h]

SIGGEN0_CTL0 is shown in Figure 20-22 and described in Table 20-22.

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Signal generator 0's control register 0

Figure 20-22 SIGGEN0_CTL0 Register
3130292827262524
RESERVED
R-0h
2322212019181716
BITLENGTH
R/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDBROUTBRINENMODE
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 20-22 SIGGEN0_CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16BITLENGTHR/W0hDefines the number bits which participates in the shift rotate operations.

Reset type: SYSRSn

15-7RESERVEDR0hReserved
6BROUTR/W0h0 : No bit reversal on data output from data transform block
1 : Perform bit reversal on data output from data transform block

Reset type: SYSRSn

5BRINR/W0h0 : No bit reversal on data input of data transform block
1 : Perform bit reversal on data input of data transform block

Reset type: SYSRSn

4ENR/W0h0 : Signal generator is disabled.
1 : Signal generator is enabled, signal generator functions as per the mode definition.

Reset type: SYSRSn

3-0MODER/W0h0 : BIT_BANG mode, The value written into DATA0 and DATA1 registers appear on the signal generator outputs as is.
1 : SHIFT_RIGHT_ONCE mode, The data value written into (DATA1,DATA0) registers are shifted right by 1 on every clock. Shifting operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared.
2 : ROTATE_RIGHT_ONCE, The data value written into (DATA1,DATA0) registers are rotated right by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared.
3 : ROTATE_RIGHT_REPEAT, The data value written into (DATA1,DATA0) registers are rotated right by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations continue until SIGGEN0_CTL0.EN bit is cleared.
4 : SHIFT_LEFT_ONCE mode, The data value written into (DATA1,DATA0) registers are shifted left by 1 on every clock. Shifting operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared.
5 : ROTATE_LEFT_ONCE, The data value written into (DATA1,DATA0) registers are rotated left by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations stops when BITLENGTH shifts are done and SIGGEN0_CTL0.EN bit is cleared.
6 : ROTATE_LEFT_REPEAT, The data value written into (DATA1,DATA0) registers are rotated left by 1 on every clock. Rotation happens within (DATA1,DATA0)[BITLENGTH-1:0] Rotate operations continue until SIGGEN0_CTL0.EN bit is cleared.
7 : SHIFT_RIGHT_REPEAT mode, The data value written into (DATA1,DATA0) registers are shifted right by 1 on every clock. Shifting operations stops when SIGGEN0_CTL0.EN bit is cleared.
8 : SHIFT_LEFT_REPEAT mode, The data value written into (DATA1,DATA0) registers are shifted left by 1 on every clock. Shifting operations stops when SIGGEN0_CTL0.EN bit is cleared.

Reset type: SYSRSn

20.8.2.16 SIGGEN0_CTL1 Register (Offset = 32h) [Reset = 00000000h]

SIGGEN0_CTL1 is shown in Figure 20-23 and described in Table 20-23.

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Signal generator 0's control register 1

Figure 20-23 SIGGEN0_CTL1 Register
31302928272625242322212019181716
DATA63_INSELRESERVED
R/W-0hR-0h
1514131211109876543210
RESERVEDDATA0_INSEL
R-0hR/W-0h
Table 20-23 SIGGEN0_CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28DATA63_INSELR/W0hSource input of bit 63 of Data register. If 0 delects DATA_NEXT[63] else, selects one of the EPGIN inputs. This provides the ability to capture the data.
0x0 : DATA_NEXT[63]
0x1 : EPGIN0
0x2 : EPGIN1
0x3 : EPGIN2
0x4 : EPGIN3
0x5 : EPGIN4
0x6 : EPGIN5
0x7 : EPGIN6
0x8 : EPGIN7
0x9-0xF : 0

Reset type: SYSRSn

27-4RESERVEDR0hReserved
3-0DATA0_INSELR/W0hSource input of bit 0 of Data register. If 0 delects DATA_NEXT[0] else, selects one of the EPGIN inputs. This provides the ability to capture the data.
0x0 : DATA_NEXT[0]
0x1 : EPGIN0
0x2 : EPGIN1
0x3 : EPGIN2
0x4 : EPGIN3
0x5 : EPGIN4
0x6 : EPGIN5
0x7 : EPGIN6
0x8 : EPGIN7
0x9-0xF : 0

Reset type: SYSRSn

20.8.2.17 SIGGEN0_DATA0 Register (Offset = 38h) [Reset = 00000000h]

SIGGEN0_DATA0 is shown in Figure 20-24 and described in Table 20-24.

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Signal generator 0's data register 0

Figure 20-24 SIGGEN0_DATA0 Register
313029282726252423222120191817161514131211109876543210
SIGGEN_DATA0
R/W-0h
Table 20-24 SIGGEN0_DATA0 Register Field Descriptions
BitFieldTypeResetDescription
31-0SIGGEN_DATA0R/W0hData used in signal bit stream. {SIGGEN_DATA1,SIGGEN_DATA0} together constitures a 64 bit data stream, which are modified as per the SIGGENx_CTL0.MODE configuration.

Reset type: SYSRSn

20.8.2.18 SIGGEN0_DATA1 Register (Offset = 3Ah) [Reset = 00000000h]

SIGGEN0_DATA1 is shown in Figure 20-25 and described in Table 20-25.

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Signal generator 0's data register 1

Figure 20-25 SIGGEN0_DATA1 Register
313029282726252423222120191817161514131211109876543210
SIGGEN_DATA1
R/W-0h
Table 20-25 SIGGEN0_DATA1 Register Field Descriptions
BitFieldTypeResetDescription
31-0SIGGEN_DATA1R/W0hData used in signal bit stream. {SIGGEN_DATA1,SIGGEN_DATA0} together constitures a 64 bit data stream, which are modified as per the SIGGENx_CTL0.MODE configuration.

Reset type: SYSRSn

20.8.2.19 SIGGEN0_DATA0_ACTIVE Register (Offset = 3Ch) [Reset = 00000000h]

SIGGEN0_DATA0_ACTIVE is shown in Figure 20-26 and described in Table 20-26.

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Signal generator 0's data active register 0

Figure 20-26 SIGGEN0_DATA0_ACTIVE Register
313029282726252423222120191817161514131211109876543210
SIGEN_DATA0
R-0h
Table 20-26 SIGGEN0_DATA0_ACTIVE Register Field Descriptions
BitFieldTypeResetDescription
31-0SIGEN_DATA0R0hThis is the lower 32 bits of the 64 bit active register (used in data transformation)

Reset type: SYSRSn

20.8.2.20 SIGGEN0_DATA1_ACTIVE Register (Offset = 3Eh) [Reset = 00000000h]

SIGGEN0_DATA1_ACTIVE is shown in Figure 20-27 and described in Table 20-27.

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Signal generator 0's data active register 1

Figure 20-27 SIGGEN0_DATA1_ACTIVE Register
313029282726252423222120191817161514131211109876543210
SIGGEN_DATA1
R-0h
Table 20-27 SIGGEN0_DATA1_ACTIVE Register Field Descriptions
BitFieldTypeResetDescription
31-0SIGGEN_DATA1R0hThis is the upper 32 bits of the 64 bit active register (used in data transformation)

Reset type: SYSRSn