SPRUIZ1B July   2023  – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 C28x System Control and Interrupts
    1. 3.1  C28x System Control Introduction
      1. 3.1.1 SYSCTL Related Collateral
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.3.4  Power-On Reset (POR)
      5. 3.3.5  Debugger Reset (SYSRS)
      6. 3.3.6  Simulate CPU1 Reset (SIMRESET)
      7. 3.3.7  Watchdog Reset (WDRS)
      8. 3.3.8  NMI Watchdog Reset (NMIWDRS)
      9. 3.3.9  Secure Code Copy Reset (SCCRESET)
      10. 3.3.10 EtherCAT SubDevice Controller (ESC) Module Reset Output
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 System Error Interrupts
      7. 3.4.7 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
        4. 3.5.3.4 ROM Uncorrectable Error
        5. 3.5.3.5 NMI Vector Fetch Mismatch
        6. 3.5.3.6 CPU2 Watchdog or NMI Watchdog Reset
        7. 3.5.3.7 EtherCAT Reset Out
        8. 3.5.3.8 CRC Fail
        9. 3.5.3.9 ERAD NMI
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check
      3. 3.6.3 NMIWDs
      4. 3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection
      5. 3.6.5 ECC Enabled Flash Memory
      6. 3.6.6 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 External Clock Output (XCLKOUT)
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Using an External Crystal or Resonator
        1. 3.7.6.1 X1/X2 Precondition Circuit
      7. 3.7.7 PLL/AUXPLL
        1. 3.7.7.1 System Clock Setup
        2. 3.7.7.2 USB Auxiliary Clock Setup
        3. 3.7.7.3 SYS PLL/AUX PLL Bypass
      8. 3.7.8 Clock (OSCCLK) Failure Detection
        1. 3.7.8.1 Missing Clock Detection Logic
    8. 3.8  Clock Configuration Semaphore
    9. 3.9  32-Bit CPU Timers 0/1/2
    10. 3.10 Watchdog Timers
      1. 3.10.1 Servicing the Watchdog Timer
      2. 3.10.2 Minimum Window Check
      3. 3.10.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.10.4 Watchdog Operation in Low-Power Modes
      5. 3.10.5 Emulation Considerations
    11. 3.11 Low-Power Modes
      1. 3.11.1 IDLE
      2. 3.11.2 STANDBY
      3. 3.11.3 HALT
    12. 3.12 Memory Controller Module
      1. 3.12.1  Dedicated RAM (Dx RAM)
      2. 3.12.2  Local Shared RAM (LSx RAM)
      3. 3.12.3  Global Shared RAM (GSx RAM)
      4. 3.12.4  CPU Message RAM (CPU MSG RAM)
      5. 3.12.5  CLA Message RAM (CLA MSGRAM)
      6. 3.12.6  CLA-DMA MSG RAM
      7. 3.12.7  Access Arbitration
      8. 3.12.8  Access Protection
        1. 3.12.8.1 CPU Fetch Protection
        2. 3.12.8.2 CPU Write Protection
        3. 3.12.8.3 CPU Read Protection
        4. 3.12.8.4 CLA Fetch Protection
        5. 3.12.8.5 CLA Write Protection
        6. 3.12.8.6 CLA Read Protection
        7. 3.12.8.7 DMA Write Protection
      9. 3.12.9  Memory Error Detection, Correction, and Error Handling
        1. 3.12.9.1 Error Detection and Correction
        2. 3.12.9.2 Error Handling
      10. 3.12.10 Application Test Hooks for Error Detection and Correction
      11. 3.12.11 ROM Test
      12. 3.12.12 RAM Initialization
    13. 3.13 JTAG
      1. 3.13.1 JTAG Noise and TAP_STATUS
    14. 3.14 Live Firmware Update (LFU)
      1. 3.14.1 LFU Background
      2. 3.14.2 LFU Switchover Steps
      3. 3.14.3 Device Features Supporting LFU
        1. 3.14.3.1 Multi-Bank Flash
        2. 3.14.3.2 PIE Vector Table Swap
        3. 3.14.3.3 LS0/LS1 RAM Memory Swap for CPU1
          1. 3.14.3.3.1 Applicability to CLA LFU
        4. 3.14.3.4 D2/D3 RAM Memory Swap for CPU2
        5. 3.14.3.5 Additional Points Pertaining to LS0/LS1 and D2/D3 RAM Memory Swap
      4. 3.14.4 LFU Switchover
      5. 3.14.5 LFU Resources
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 MCU Configuration (MCUCNFx)
    17. 3.17 Software
      1. 3.17.1 SYSCTL Examples
        1. 3.17.1.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.17.1.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      2. 3.17.2 MEMCFG Examples
        1. 3.17.2.1 Correctable & Uncorrectable Memory Error Handling
        2. 3.17.2.2 Shared RAM Management (CPU1) - C28X_DUAL
        3. 3.17.2.3 Shared RAM Management (CPU2) - C28X_DUAL
      3. 3.17.3 NMI Examples
        1. 3.17.3.1 NMI handling - C28X_DUAL
        2. 3.17.3.2 Watchdog Reset - C28X_DUAL
      4. 3.17.4 TIMER Examples
        1. 3.17.4.1 CPU Timers - SINGLE_CORE
        2. 3.17.4.2 CPU Timers - SINGLE_CORE
      5. 3.17.5 WATCHDOG Examples
        1. 3.17.5.1 Watchdog - SINGLE_CORE
    18. 3.18 System Control Registers
      1. 3.18.1  SYSCTRL Base Address Table
      2. 3.18.2  LFU Base Address Table
      3. 3.18.3  CPUTIMER_REGS Registers
      4. 3.18.4  PIE_CTRL_REGS Registers
      5. 3.18.5  WD_REGS Registers
      6. 3.18.6  NMI_INTRUPT_REGS Registers
      7. 3.18.7  XINT_REGS Registers
      8. 3.18.8  SYNC_SOC_REGS Registers
      9. 3.18.9  CPU1_DMA_CLA_SRC_SEL_REGS Registers
      10. 3.18.10 CPU2_DMA_CLA_SRC_SEL_REGS Registers
      11. 3.18.11 DEV_CFG_REGS Registers
      12. 3.18.12 CLK_CFG_REGS Registers
      13. 3.18.13 CPU1_SYS_REGS Registers
      14. 3.18.14 CPU2_SYS_REGS Registers
      15. 3.18.15 CPU1_SYS_STATUS_REGS Registers
      16. 3.18.16 CPU2_SYS_STATUS_REGS Registers
      17. 3.18.17 CPU1_PERIPH_AC_REGS Registers
      18. 3.18.18 CPU2_PERIPH_AC_REGS Registers
      19. 3.18.19 MEM_CFG_REGS Registers
      20. 3.18.20 ACCESS_PROTECTION_REGS Registers
      21. 3.18.21 MEMORY_ERROR_REGS Registers
      22. 3.18.22 ROM_WAIT_STATE_REGS Registers
      23. 3.18.23 TEST_ERROR_REGS Registers
      24. 3.18.24 UID_REGS Registers
      25. 3.18.25 CPU1_LFU_REGS Registers
      26. 3.18.26 CPU2_LFU_REGS Registers
      27. 3.18.27 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      28. 3.18.28 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      29. 3.18.29 CPU2_DMA_CLA_SRC_SEL_REGS Registers
      30. 3.18.30 Register to Driverlib Function Mapping
        1. 3.18.30.1 ASYSCTL Registers to Driverlib Functions
        2. 3.18.30.2 CPUTIMER Registers to Driverlib Functions
        3. 3.18.30.3 MEMCFG Registers to Driverlib Functions
        4. 3.18.30.4 NMI Registers to Driverlib Functions
        5. 3.18.30.5 PIE Registers to Driverlib Functions
        6. 3.18.30.6 SYSCTL Registers to Driverlib Functions
        7. 3.18.30.7 WWD Registers to Driverlib Functions
        8. 3.18.30.8 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.7.2  Booting CPU2
        1. 4.7.2.1 Boot Up Procedure
        2. 4.7.2.2 IPCBOOTMODE Details
        3. 4.7.2.3 Error IPC Command Table
      3. 4.7.3  Entry Points
      4. 4.7.4  Wait Points
      5. 4.7.5  Secure Flash Boot Mode
        1. 4.7.5.1 Secure Flash CPU1 Linker File Example
      6. 4.7.6  Memory Maps
        1. 4.7.6.1 Boot ROM Memory-Maps
        2. 4.7.6.2 Reserved RAM Memory-Maps
      7. 4.7.7  ROM Tables
      8. 4.7.8  Boot Modes and Loaders
        1. 4.7.8.1 Boot Modes
          1. 4.7.8.1.1 Flash Boot
          2. 4.7.8.1.2 RAM Boot
          3. 4.7.8.1.3 Wait Boot
          4. 4.7.8.1.4 Secure LFU Flash Boot
        2. 4.7.8.2 Bootloaders
          1. 4.7.8.2.1 SCI Boot Mode
          2. 4.7.8.2.2 SPI Boot Mode
          3. 4.7.8.2.3 I2C Boot Mode
          4. 4.7.8.2.4 Parallel Boot Mode
          5. 4.7.8.2.5 CAN Boot Mode
          6. 4.7.8.2.6 CAN-FD Boot Mode
          7. 4.7.8.2.7 USB Boot Mode
          8. 4.7.8.2.8 IPC Message Copy to RAM Boot
          9. 4.7.8.2.9 Firmware Update (FWU) Flash Boot
      9. 4.7.9  GPIO Assignments
      10. 4.7.10 Secure ROM Function APIs
      11. 4.7.11 Clock Initializations
      12. 4.7.12 Boot Status Information
        1. 4.7.12.1 Booting Status
        2. 4.7.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      13. 4.7.13 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
        2. 5.8.1.2 DCSM Memory partitioning Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
      7. 5.9.7 DCSM Registers to Driverlib Functions
  8. 6 Background CRC-32 (BGCRC)
    1. 6.1 Introduction
      1. 6.1.1 BGCRC Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Block Diagram
      4. 6.1.4 Memory Wait States and Memory Map
    2. 6.2 Functional Description
      1. 6.2.1 Data Read Unit
      2. 6.2.2 CRC-32 Compute Unit
      3. 6.2.3 CRC Notification Unit
        1. 6.2.3.1 CPU Interrupt and NMI
      4. 6.2.4 Operating Modes
        1. 6.2.4.1 CRC Mode
        2. 6.2.4.2 Scrub Mode
      5. 6.2.5 BGCRC Watchdog
      6. 6.2.6 Hardware and Software Faults Protection
    3. 6.3 Application of the BGCRC
      1. 6.3.1 Software Configuration
      2. 6.3.2 Decision on Error Response Severity
      3. 6.3.3 Decision of Controller for CLA_CRC
      4. 6.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 6.3.5 BGCRC Execution
      6. 6.3.6 Debug/Error Response for BGCRC Errors
      7. 6.3.7 BGCRC Golden CRC-32 Value Computation
    4. 6.4 Software
      1. 6.4.1 BGCRC Examples
        1. 6.4.1.1 BGCRC CPU Interrupt Example
        2. 6.4.1.2 BGCRC Example with Watchdog and Lock
        3. 6.4.1.3 CLA-BGCRC Example in CRC mode
        4. 6.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 6.5 BGCRC Registers
      1. 6.5.1 BGCRC Base Address Table
      2. 6.5.2 BGCRC_REGS Registers
      3. 6.5.3 BGCRC Registers to Driverlib Functions
  9. 7 Control Law Accelerator (CLA)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 CLA Related Collateral
      3. 7.1.3 Block Diagram
    2. 7.2 CLA Interface
      1. 7.2.1 CLA Memory
      2. 7.2.2 CLA Memory Bus
      3. 7.2.3 Shared Peripherals and EALLOW Protection
      4. 7.2.4 CLA Tasks and Interrupt Vectors
      5. 7.2.5 CLA Software Interrupt to CPU
    3. 7.3 CLA, DMA, and CPU Arbitration
      1. 7.3.1 CLA Message RAM
      2. 7.3.2 CLA Program Memory
      3. 7.3.3 CLA Data Memory
      4. 7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 7.4 CLA Configuration and Debug
      1. 7.4.1 Building a CLA Application
      2. 7.4.2 Typical CLA Initialization Sequence
      3. 7.4.3 Debugging CLA Code
        1. 7.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 7.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)
      4. 7.4.4 CLA Illegal Opcode Behavior
      5. 7.4.5 Resetting the CLA
    5. 7.5 Pipeline
      1. 7.5.1 Pipeline Overview
      2. 7.5.2 CLA Pipeline Alignment
        1. 7.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       383
        3. 7.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       385
        5. 7.5.2.3 ADC Early Interrupt to CLA Response
      3. 7.5.3 Parallel Instructions
        1. 7.5.3.1 Math Operation with Parallel Load
        2. 7.5.3.2 Multiply with Parallel Add
      4. 7.5.4 CLA Task Execution Latency
    6. 7.6 Software
      1. 7.6.1 CLA Examples
        1. 7.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 7.6.1.2 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        3. 7.6.1.3 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        4. 7.6.1.4 CLA background nesting task
        5. 7.6.1.5 Controlling PWM output using CLA
        6. 7.6.1.6 Just-in-time ADC sampling with CLA
        7. 7.6.1.7 Optimal offloading of control algorithms to CLA
        8. 7.6.1.8 Handling shared resources across C28x and CLA
    7. 7.7 Instruction Set
      1. 7.7.1 Instruction Descriptions
      2. 7.7.2 Addressing Modes and Encoding
      3. 7.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCLRC BGINTM
        13.       MCMP32 MRa, MRb
        14.       MCMPF32 MRa, MRb
        15.       MCMPF32 MRa, #16FHi
        16.       MDEBUGSTOP
        17.       MDEBUGSTOP1
        18.       MEALLOW
        19.       MEDIS
        20.       MEINVF32 MRa, MRb
        21.       MEISQRTF32 MRa, MRb
        22.       MF32TOI16 MRa, MRb
        23.       MF32TOI16R MRa, MRb
        24.       MF32TOI32 MRa, MRb
        25.       MF32TOUI16 MRa, MRb
        26.       MF32TOUI16R MRa, MRb
        27.       MF32TOUI32 MRa, MRb
        28.       MFRACF32 MRa, MRb
        29.       MI16TOF32 MRa, MRb
        30.       MI16TOF32 MRa, mem16
        31.       MI32TOF32 MRa, mem32
        32.       MI32TOF32 MRa, MRb
        33.       MLSL32 MRa, #SHIFT
        34.       MLSR32 MRa, #SHIFT
        35.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        36.       MMAXF32 MRa, MRb
        37.       MMAXF32 MRa, #16FHi
        38.       MMINF32 MRa, MRb
        39.       MMINF32 MRa, #16FHi
        40.       MMOV16 MARx, MRa, #16I
        41.       MMOV16 MARx, mem16
        42.       MMOV16 mem16, MARx
        43.       MMOV16 mem16, MRa
        44.       MMOV32 mem32, MRa
        45.       MMOV32 mem32, MSTF
        46.       MMOV32 MRa, mem32 [, CNDF]
        47.       MMOV32 MRa, MRb [, CNDF]
        48.       MMOV32 MSTF, mem32
        49.       MMOVD32 MRa, mem32
        50.       MMOVF32 MRa, #32F
        51.       MMOVI16 MARx, #16I
        52.       MMOVI32 MRa, #32FHex
        53.       MMOVIZ MRa, #16FHi
        54.       MMOVZ16 MRa, mem16
        55.       MMOVXI MRa, #16FLoHex
        56.       MMPYF32 MRa, MRb, MRc
        57.       MMPYF32 MRa, #16FHi, MRb
        58.       MMPYF32 MRa, MRb, #16FHi
        59.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        60.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        61.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        62.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        63.       MNEGF32 MRa, MRb[, CNDF]
        64.       MNOP
        65.       MOR32 MRa, MRb, MRc
        66.       MRCNDD [CNDF]
        67.       MSETC BGINTM
        68.       MSETFLG FLAG, VALUE
        69.       MSTOP
        70.       MSUB32 MRa, MRb, MRc
        71.       MSUBF32 MRa, MRb, MRc
        72.       MSUBF32 MRa, #16FHi, MRb
        73.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        74.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        75.       MSWAPF MRa, MRb [, CNDF]
        76.       MTESTTF CNDF
        77.       MUI16TOF32 MRa, mem16
        78.       MUI16TOF32 MRa, MRb
        79.       MUI32TOF32 MRa, mem32
        80.       MUI32TOF32 MRa, MRb
        81.       MXOR32 MRa, MRb, MRc
    8. 7.8 CLA Registers
      1. 7.8.1 CLA Base Address Table
      2. 7.8.2 CLA_ONLY_REGS Registers
      3. 7.8.3 CLA_SOFTINT_REGS Registers
      4. 7.8.4 CLA_REGS Registers
      5. 7.8.5 CLA Registers to Driverlib Functions
  10. 8 Configurable Logic Block (CLB)
    1. 8.1  Introduction
      1. 8.1.1 CLB Related Collateral
    2. 8.2  Description
      1. 8.2.1 CLB Clock
    3. 8.3  CLB Input/Output Connection
      1. 8.3.1 Overview
      2. 8.3.2 CLB Input Selection
      3. 8.3.3 CLB Output Selection
      4. 8.3.4 CLB Output Signal Multiplexer
    4. 8.4  CLB Tile
      1. 8.4.1 Static Switch Block
      2. 8.4.2 Counter Block
        1. 8.4.2.1 Counter Description
        2. 8.4.2.2 Counter Operation
        3. 8.4.2.3 Serializer Mode
        4. 8.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 8.4.3 FSM Block
      4. 8.4.4 LUT4 Block
      5. 8.4.5 Output LUT Block
      6. 8.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 8.4.7 High Level Controller (HLC)
        1. 8.4.7.1 High Level Controller Events
        2. 8.4.7.2 High Level Controller Instructions
        3. 8.4.7.3 <Src> and <Dest>
        4. 8.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 8.5  CPU Interface
      1. 8.5.1 Register Description
      2. 8.5.2 Non-Memory Mapped Registers
    6. 8.6  DMA Access
    7. 8.7  CLB Data Export Through SPI RX Buffer
    8. 8.8  CLB Pipeline Mode
    9. 8.9  Software
      1. 8.9.1 CLB Examples
        1. 8.9.1.1  CLB Empty Project
        2. 8.9.1.2  CLB Combinational Logic
        3. 8.9.1.3  CLB GPIO Input Filter
        4. 8.9.1.4  CLB Auxilary PWM
        5. 8.9.1.5  CLB PWM Protection
        6. 8.9.1.6  CLB Event Window
        7. 8.9.1.7  CLB Signal Generator
        8. 8.9.1.8  CLB State Machine
        9. 8.9.1.9  CLB External Signal AND Gate
        10. 8.9.1.10 CLB Timer
        11. 8.9.1.11 CLB Timer Two States
        12. 8.9.1.12 CLB Interrupt Tag
        13. 8.9.1.13 CLB Output Intersect
        14. 8.9.1.14 CLB PUSH PULL
        15. 8.9.1.15 CLB Multi Tile
        16. 8.9.1.16 CLB Tile to Tile Delay
        17. 8.9.1.17 CLB Glue Logic
        18. 8.9.1.18 CLB based One-shot PWM
        19. 8.9.1.19 CLB AOC Control
        20. 8.9.1.20 CLB AOC Release Control
        21. 8.9.1.21 CLB XBARs
        22. 8.9.1.22 CLB AOC Control
        23. 8.9.1.23 CLB Serializer
        24. 8.9.1.24 CLB LFSR
        25. 8.9.1.25 CLB Lock Output Mask
        26. 8.9.1.26 CLB INPUT Pipeline Mode
        27. 8.9.1.27 CLB Clocking and PIPELINE Mode
        28. 8.9.1.28 CLB SPI Data Export
        29. 8.9.1.29 CLB SPI Data Export DMA
        30. 8.9.1.30 CLB Trip Zone Timestamp
        31. 8.9.1.31 CLB CRC
        32. 8.9.1.32 CLB TDM Serial Port
        33. 8.9.1.33 CLB LED Driver
    10. 8.10 CLB Registers
      1. 8.10.1 CLB Base Address Table
      2. 8.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 8.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 8.10.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 8.10.5 CLB Registers to Driverlib Functions
  11. 9 Dual-Clock Comparator (DCC)
    1. 9.1 Introduction
      1. 9.1.1 Features
      2. 9.1.2 Block Diagram
    2. 9.2 Module Operation
      1. 9.2.1 Configuring DCC Counters
      2. 9.2.2 Single-Shot Measurement Mode
      3. 9.2.3 Continuous Monitoring Mode
      4. 9.2.4 Error Conditions
    3. 9.3 Interrupts
    4. 9.4 Software
      1. 9.4.1 DCC Examples
        1. 9.4.1.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 9.4.1.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 9.4.1.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 9.5 DCC Registers
      1. 9.5.1 DCC Base Address Table
      2. 9.5.2 DCC_REGS Registers
      3. 9.5.3 DCC Registers to Driverlib Functions
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 CPU and CLA Arbitration
    6. 10.6 Channel Priority
      1. 10.6.1 Round-Robin Mode
      2. 10.6.2 Channel 1 High-Priority Mode
    7. 10.7 Overrun Detection Feature
    8. 10.8 Software
      1. 10.8.1 DMA Examples
        1. 10.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 10.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 10.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 10.9 DMA Registers
      1. 10.9.1 DMA Base Address Table
      2. 10.9.2 DMA_REGS Registers
      3. 10.9.3 DMA_CH_REGS Registers
      4. 10.9.4 DMA_CLA_SRC_SEL_REGS Registers
      5. 10.9.5 DMA Registers to Driverlib Functions
  13. 11External Memory Interface (EMIF)
    1. 11.1 Introduction
      1. 11.1.1 Purpose of the Peripheral
      2. 11.1.2 EMIF Related Collateral
      3. 11.1.3 Features
        1. 11.1.3.1 Asynchronous Memory Support
        2. 11.1.3.2 Synchronous DRAM Memory Support
      4. 11.1.4 Functional Block Diagram
      5. 11.1.5 Configuring Device Pins
    2. 11.2 EMIF Module Architecture
      1. 11.2.1  EMIF Clock Control
      2. 11.2.2  EMIF Requests
      3. 11.2.3  EMIF Signal Descriptions
      4. 11.2.4  EMIF Signal Multiplexing Control
      5. 11.2.5  SDRAM Controller and Interface
        1. 11.2.5.1  SDRAM Commands
        2. 11.2.5.2  Interfacing to SDRAM
        3. 11.2.5.3  SDRAM Configuration Registers
        4. 11.2.5.4  SDRAM Auto-Initialization Sequence
        5. 11.2.5.5  SDRAM Configuration Procedure
        6. 11.2.5.6  EMIF Refresh Controller
          1. 11.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 11.2.5.7  Self-Refresh Mode
        8. 11.2.5.8  Power-Down Mode
        9. 11.2.5.9  SDRAM Read Operation
        10. 11.2.5.10 SDRAM Write Operations
        11. 11.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 11.2.6  Asynchronous Controller and Interface
        1. 11.2.6.1 Interfacing to Asynchronous Memory
        2. 11.2.6.2 Accessing Larger Asynchronous Memories
        3. 11.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 11.2.6.4 Read and Write Operations in Normal Mode
          1. 11.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 11.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 11.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 11.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 11.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 11.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 11.2.7  Data Bus Parking
      8. 11.2.8  Reset and Initialization Considerations
      9. 11.2.9  Interrupt Support
        1. 11.2.9.1 Interrupt Events
      10. 11.2.10 DMA Event Support
      11. 11.2.11 EMIF Signal Multiplexing
      12. 11.2.12 Memory Map
      13. 11.2.13 Priority and Arbitration
      14. 11.2.14 System Considerations
        1. 11.2.14.1 Asynchronous Request Times
      15. 11.2.15 Power Management
        1. 11.2.15.1 Power Management Using Self-Refresh Mode
        2. 11.2.15.2 Power Management Using Power Down Mode
      16. 11.2.16 Emulation Considerations
    3. 11.3 Example Configuration
      1. 11.3.1 Hardware Interface
      2. 11.3.2 Software Configuration
        1. 11.3.2.1 Configuring the SDRAM Interface
          1. 11.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 11.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 11.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 11.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 11.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 11.3.2.2 Configuring the Flash Interface
          1. 11.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 11.4 Software
      1. 11.4.1 EMIF Examples
        1. 11.4.1.1 Pin setup for EMIF module accessing ASRAM.
        2. 11.4.1.2 EMIF1 ASYNC module accessing 16bit ASRAM.
        3. 11.4.1.3 EMIF1 module accessing 16bit ASRAM as code memory.
        4. 11.4.1.4 EMIF1 module accessing 16bit SDRAM using memcpy_fast_far().
        5. 11.4.1.5 EMIF1 module accessing 16bit SDRAM then puts into Self Refresh mode before entering Low Power Mode.
        6. 11.4.1.6 EMIF1 module accessing 32bit SDRAM using DMA.
        7. 11.4.1.7 EMIF1 module accessing 16bit SDRAM using alternate address mapping.
    5. 11.5 EMIF Registers
      1. 11.5.1 EMIF Base Address Table
      2. 11.5.2 EMIF_REGS Registers
      3. 11.5.3 EMIF1_CONFIG_REGS Registers
      4. 11.5.4 EMIF Registers to Driverlib Functions
  14. 12Flash Module
    1. 12.1  Introduction to Flash and OTP Memory
      1. 12.1.1 FLASH Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Flash Tools
      4. 12.1.4 Default Flash Configuration
    2. 12.2  Flash Bank, OTP, and Pump
    3. 12.3  Flash Wrapper
    4. 12.4  Flash and OTP Memory Performance
    5. 12.5  Flash Read Interface
      1. 12.5.1 C28x-Flash Read Interface
        1. 12.5.1.1 Standard Read Mode
        2. 12.5.1.2 Prefetch Mode
        3. 12.5.1.3 Data Cache
        4. 12.5.1.4 Flash Read Operation
    6. 12.6  Flash Erase and Program
      1. 12.6.1 Flash Controller Access Semaphore
      2. 12.6.2 Erase
      3. 12.6.3 Program
      4. 12.6.4 Verify
    7. 12.7  Error Correction Code (ECC) Protection
      1. 12.7.1 Single-Bit Data Error
      2. 12.7.2 Uncorrectable Error
      3. 12.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 12.8  Reserved Locations Within Flash and OTP
    9. 12.9  Migrating an Application from RAM to Flash
    10. 12.10 Procedure to Change the Flash Control Registers
    11. 12.11 Software
      1. 12.11.1 FLASH Examples
        1. 12.11.1.1 Flash Programming with 512-bit AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        2. 12.11.1.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        3. 12.11.1.3 Flash Programming with 512-bit AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        4. 12.11.1.4 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
    12. 12.12 Flash Registers
      1. 12.12.1 FLASH Base Address Table
      2. 12.12.2 FLASH_CTRL_REGS Registers
      3. 12.12.3 FLASH_ECC_REGS Registers
      4. 12.12.4 FLASH Registers to Driverlib Functions
  15. 13Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 13.1 Introduction
      1. 13.1.1 ERAD Related Collateral
    2. 13.2 Enhanced Bus Comparator Unit
      1. 13.2.1 Enhanced Bus Comparator Unit Operations
      2. 13.2.2 Event Masking and Exporting
    3. 13.3 System Event Counter Unit
      1. 13.3.1 System Event Counter Modes
        1. 13.3.1.1 Counting Active Levels Versus Edges
        2. 13.3.1.2 Max Mode
        3. 13.3.1.3 Cumulative Mode
        4. 13.3.1.4 Input Signal Selection
      2. 13.3.2 Reset on Event
      3. 13.3.3 Operation Conditions
    4. 13.4 ERAD Ownership, Initialization and Reset
    5. 13.5 ERAD Programming Sequence
      1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 13.5.2 Timer and Counter Programming Sequence
    6. 13.6 Cyclic Redundancy Check Unit
      1. 13.6.1 CRC Unit Qualifier
      2. 13.6.2 CRC Unit Programming Sequence
    7. 13.7 Program Counter Trace
      1. 13.7.1 Functional Block Diagram
      2. 13.7.2 Trace Qualification Modes
      3. 13.7.3 Trace Memory
      4. 13.7.4 Trace Input Signal Conditioning
      5. 13.7.5 PC Trace Software Operation
      6. 13.7.6 Trace Operation in Debug Mode
    8. 13.8 Software
      1. 13.8.1 ERAD Examples
        1. 13.8.1.1  ERAD Profiling Interrupts
        2. 13.8.1.2  ERAD Profile Function
        3. 13.8.1.3  ERAD Profile Function
        4. 13.8.1.4  ERAD HWBP Monitor Program Counter
        5. 13.8.1.5  ERAD HWBP Monitor Program Counter
        6. 13.8.1.6  ERAD Profile Function
        7. 13.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 13.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 13.8.1.9  ERAD Stack Overflow
        10. 13.8.1.10 ERAD Profile Interrupts CLA
        11. 13.8.1.11 ERAD Profiling Interrupts
        12. 13.8.1.12 ERAD Profiling Interrupts
        13. 13.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 13.8.1.14 ERAD INTERRUPT ORDER
        15. 13.8.1.15 ERAD AND CLB
        16. 13.8.1.16 ERAD PWM PROTECTION
    9. 13.9 ERAD Registers
      1. 13.9.1 ERAD Base Address Table
      2. 13.9.2 ERAD_GLOBAL_REGS Registers
      3. 13.9.3 ERAD_HWBP_REGS Registers
      4. 13.9.4 ERAD_COUNTER_REGS Registers
      5. 13.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 13.9.6 ERAD_CRC_REGS Registers
      7. 13.9.7 PCTRACE_REGS Registers
      8. 13.9.8 PCTRACE_BUFFER_REGS Registers
      9. 13.9.9 ERAD Registers to Driverlib Functions
  16. 14General-Purpose Input/Output (GPIO)
    1. 14.1  Introduction
      1. 14.1.1 GPIO Related Collateral
    2. 14.2  Configuration Overview
    3. 14.3  Digital Inputs on ADC Pins (AIOs)
    4. 14.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 14.5  Digital General-Purpose I/O Control
    6. 14.6  Input Qualification
      1. 14.6.1 No Synchronization (Asynchronous Input)
      2. 14.6.2 Synchronization to SYSCLKOUT Only
      3. 14.6.3 Qualification Using a Sampling Window
    7. 14.7  USB Signals
    8. 14.8  GPIO and Peripheral Muxing
      1. 14.8.1 GPIO Muxing
      2. 14.8.2 Peripheral Muxing
    9. 14.9  Internal Pullup Configuration Requirements
    10. 14.10 Software
      1. 14.10.1 GPIO Examples
        1. 14.10.1.1 Device GPIO Toggle - SINGLE_CORE
        2. 14.10.1.2 XINT/XBAR example - SINGLE_CORE
      2. 14.10.2 LED Examples
        1. 14.10.2.1 LED Blinky Example - MULTI_CORE
        2. 14.10.2.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 14.10.2.3 LED Blinky example - SINGLE_CORE
        4. 14.10.2.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 14.10.2.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 14.10.2.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 14.11 GPIO Registers
      1. 14.11.1 GPIO Base Address Table
      2. 14.11.2 GPIO_CTRL_REGS Registers
      3. 14.11.3 GPIO_DATA_REGS Registers
      4. 14.11.4 GPIO_DATA_READ_REGS Registers
      5. 14.11.5 GPIO Registers to Driverlib Functions
  17. 15Interprocessor Communication (IPC)
    1. 15.1 Introduction
    2. 15.2 Message RAMs
    3. 15.3 IPC Flags and Interrupts
    4. 15.4 IPC Command Registers
    5. 15.5 Free-Running Counter
    6. 15.6 IPC Communication Protocol
    7. 15.7 Software
      1. 15.7.1 IPC Examples
        1. 15.7.1.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 15.7.1.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 15.7.1.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 15.7.1.4 IPC basic message passing example with interrupt - MULTI_CORE
    8. 15.8 IPC Registers
      1. 15.8.1 IPC Base Address Table
      2. 15.8.2 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      3. 15.8.3 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      4. 15.8.4 IPC Registers to Driverlib Functions
  18. 16Crossbar (X-BAR)
    1. 16.1 Input X-BAR, ICL XBAR, MINDB XBAR, and CLB Input X-BAR
      1. 16.1.1 CLB Input X-BAR
      2. 16.1.2 ICL and MINDB X-BAR
    2. 16.2 ePWM , CLB, and GPIO Output X-BAR
      1. 16.2.1 ePWM X-BAR
        1. 16.2.1.1 ePWM X-BAR Architecture
      2. 16.2.2 CLB X-BAR
        1. 16.2.2.1 CLB X-BAR Architecture
      3. 16.2.3 GPIO Output X-BAR
        1. 16.2.3.1 GPIO Output X-BAR Architecture
      4. 16.2.4 CLB Output X-BAR
        1. 16.2.4.1 CLB Output X-BAR Architecture
      5. 16.2.5 X-BAR Flags
    3. 16.3 XBAR Registers
      1. 16.3.1  XBAR Base Address Table
      2. 16.3.2  EPWM_XBAR_REGS Registers
      3. 16.3.3  INPUT_XBAR_REGS Registers
      4. 16.3.4  XBAR_REGS Registers
      5. 16.3.5  MINDB_XBAR_REGS Registers
      6. 16.3.6  ICL_XBAR_REGS Registers
      7. 16.3.7  CLB_XBAR_REGS Registers
      8. 16.3.8  OUTPUT_XBAR_EXT64_REGS Registers
      9. 16.3.9  OUTPUT_XBAR_REGS Registers
      10. 16.3.10 Register to Driverlib Function Mapping
        1. 16.3.10.1 EPWMXBAR Registers to Driverlib Functions
        2. 16.3.10.2 INPUTXBAR Registers to Driverlib Functions
        3. 16.3.10.3 XBAR Registers to Driverlib Functions
        4. 16.3.10.4 MINDBXBAR Registers to Driverlib Functions
        5. 16.3.10.5 ICLXBAR Registers to Driverlib Functions
        6. 16.3.10.6 CLBXBAR Registers to Driverlib Functions
        7. 16.3.10.7 OUTPUTXBAR Registers to Driverlib Functions
  19. 17Analog Subsystem
    1. 17.1 Introduction
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
    2. 17.2 Optimizing Power-Up Time
    3. 17.3 Digital Inputs on ADC Pins (AIOs)
    4. 17.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 17.5 Analog Subsystem Registers
      1. 17.5.1 ASBSYS Base Address Table
      2. 17.5.2 ANALOG_SUBSYS_REGS Registers
  20. 18Analog-to-Digital Converter (ADC)
    1. 18.1  Introduction
      1. 18.1.1 ADC Related Collateral
      2. 18.1.2 Features
      3. 18.1.3 Block Diagram
    2. 18.2  ADC Configurability
      1. 18.2.1 Clock Configuration
      2. 18.2.2 Resolution
      3. 18.2.3 Voltage Reference
        1. 18.2.3.1 External Reference Mode
        2. 18.2.3.2 Internal Reference Mode
        3. 18.2.3.3 Ganged References
        4. 18.2.3.4 Selecting Reference Mode
      4. 18.2.4 Signal Mode
      5. 18.2.5 Expected Conversion Results
      6. 18.2.6 Interpreting Conversion Results
    3. 18.3  SOC Principle of Operation
      1. 18.3.1 SOC Configuration
      2. 18.3.2 Trigger Operation
        1. 18.3.2.1 Global Software Trigger
        2. 18.3.2.2 Trigger Repeaters
          1. 18.3.2.2.1 Oversampling Mode
          2. 18.3.2.2.2 Undersampling Mode
          3. 18.3.2.2.3 Trigger Phase Delay
          4. 18.3.2.2.4 Re-trigger Spread
          5. 18.3.2.2.5 Trigger Repeater Configuration
            1. 18.3.2.2.5.1 Register Shadow Updates
          6. 18.3.2.2.6 Re-Trigger Logic
          7. 18.3.2.2.7 Multi-Path Triggering Behavior
      3. 18.3.3 ADC Acquisition (Sample and Hold) Window
      4. 18.3.4 ADC Input Models
      5. 18.3.5 Channel Selection
        1. 18.3.5.1 External Channel Selection
          1. 18.3.5.1.1 External Channel Selection Timing
    4. 18.4  SOC Configuration Examples
      1. 18.4.1 Single Conversion from ePWM Trigger
      2. 18.4.2 Oversampled Conversion from ePWM Trigger
      3. 18.4.3 Multiple Conversions from CPU Timer Trigger
      4. 18.4.4 Software Triggering of SOCs
    5. 18.5  ADC Conversion Priority
    6. 18.6  Burst Mode
      1. 18.6.1 Burst Mode Example
      2. 18.6.2 Burst Mode Priority Example
    7. 18.7  EOC and Interrupt Operation
      1. 18.7.1 Interrupt Overflow
      2. 18.7.2 Continue to Interrupt Mode
      3. 18.7.3 Early Interrupt Configuration Mode
    8. 18.8  Post-Processing Blocks
      1. 18.8.1 PPB Offset Correction
      2. 18.8.2 PPB Error Calculation
      3. 18.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 18.8.4 PPB Sample Delay Capture
      5. 18.8.5 PPB Oversampling
        1. 18.8.5.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 18.8.5.2 Outlier Rejection
    9. 18.9  Result Safety Checker
      1. 18.9.1 Result Safety Checker Operation
      2. 18.9.2 Result Safety Checker Interrupts and Events
    10. 18.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 18.10.1 Implementation
      2. 18.10.2 Detecting an Open Input Pin
      3. 18.10.3 Detecting a Shorted Input Pin
    11. 18.11 Power-Up Sequence
    12. 18.12 ADC Calibration
      1. 18.12.1 ADC Zero Offset Calibration
    13. 18.13 ADC Timings
      1. 18.13.1 ADC Timing Diagrams
      2. 18.13.2 Post-Processing Block Timings
    14. 18.14 Additional Information
      1. 18.14.1 Ensuring Synchronous Operation
        1. 18.14.1.1 Basic Synchronous Operation
        2. 18.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 18.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 18.14.1.4 Synchronous Operation with Different Resolutions
        5. 18.14.1.5 Non-overlapping Conversions
      2. 18.14.2 Choosing an Acquisition Window Duration
      3. 18.14.3 Achieving Simultaneous Sampling
      4. 18.14.4 Result Register Mapping
      5. 18.14.5 Internal Temperature Sensor
      6. 18.14.6 Designing an External Reference Circuit
      7. 18.14.7 ADC-DAC Loopback Testing
      8. 18.14.8 Internal Test Mode
      9. 18.14.9 ADC Gain and Offset Calibration
    15. 18.15 Software
      1. 18.15.1 ADC Examples
        1. 18.15.1.1  ADC Software Triggering - SINGLE_CORE
        2. 18.15.1.2  ADC ePWM Triggering - SINGLE_CORE
        3. 18.15.1.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 18.15.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 18.15.1.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 18.15.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 18.15.1.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 18.15.1.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 18.15.1.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 18.15.1.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 18.15.1.11 ADC Burst Mode - SINGLE_CORE
        12. 18.15.1.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 18.15.1.13 ADC SOC Oversampling - SINGLE_CORE
        14. 18.15.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 18.15.1.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 18.15.1.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 18.15.1.17 ADC Safety Checker - SINGLE_CORE
    16. 18.16 ADC Registers
      1. 18.16.1 ADC Base Address Table
      2. 18.16.2 ADC_RESULT_REGS Registers
      3. 18.16.3 ADC_REGS Registers
      4. 18.16.4 ADC_SAFECHECK_INTEVT_REGS Registers
      5. 18.16.5 ADC_SAFECHECK_REGS Registers
      6. 18.16.6 ADC Registers to Driverlib Functions
  21. 19Buffered Digital-to-Analog Converter (DAC)
    1. 19.1 Introduction
      1. 19.1.1 DAC Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Block Diagram
    2. 19.2 Using the DAC
      1. 19.2.1 Initialization Sequence
      2. 19.2.2 DAC Offset Adjustment
      3. 19.2.3 EPWMSYNCPER Signal
    3. 19.3 Lock Registers
    4. 19.4 Software
      1. 19.4.1 DAC Examples
        1. 19.4.1.1 Buffered DAC Enable - SINGLE_CORE
        2. 19.4.1.2 Buffered DAC Random - SINGLE_CORE
    5. 19.5 DAC Registers
      1. 19.5.1 DAC Base Address Table
      2. 19.5.2 DAC_REGS Registers
      3. 19.5.3 DAC Registers to Driverlib Functions
  22. 20Comparator Subsystem (CMPSS)
    1. 20.1 Introduction
      1. 20.1.1 CMPSS Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Block Diagram
    2. 20.2 Comparator
    3. 20.3 Reference DAC
    4. 20.4 Ramp Generator
      1. 20.4.1 Ramp Generator Overview
      2. 20.4.2 Ramp Generator Behavior
      3. 20.4.3 Ramp Generator Behavior at Corner Cases
    5. 20.5 Digital Filter
      1. 20.5.1 Filter Initialization Sequence
    6. 20.6 Using the CMPSS
      1. 20.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 20.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 20.6.3 Calibrating the CMPSS
      4. 20.6.4 Enabling and Disabling the CMPSS Clock
    7. 20.7 Software
      1. 20.7.1 CMPSS Examples
        1. 20.7.1.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 20.7.1.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 20.8 CMPSS Registers
      1. 20.8.1 CMPSS Base Address Table
      2. 20.8.2 CMPSS_REGS Registers
      3. 20.8.3 CMPSS Registers to Driverlib Functions
  23. 21Enhanced Capture (eCAP) and High Resolution Capture (HRCAP)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 ECAP Related Collateral
    2. 21.2  Description
    3. 21.3  Configuring Device Pins for the eCAP
    4. 21.4  Capture and APWM Operating Mode
    5. 21.5  Capture Mode Description
      1. 21.5.1  Event Prescaler
      2. 21.5.2  Glitch Filter
      3. 21.5.3  Edge Polarity Select and Qualifier
      4. 21.5.4  Continuous/One-Shot Control
      5. 21.5.5  32-Bit Counter and Phase Control
      6. 21.5.6  CAP1-CAP4 Registers
      7. 21.5.7  eCAP Synchronization
        1. 21.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 21.5.8  Interrupt Control
      9. 21.5.9  DMA Interrupt
      10. 21.5.10 ADC SOC Event
      11. 21.5.11 Shadow Load and Lockout Control
      12. 21.5.12 APWM Mode Operation
      13. 21.5.13 Signal Monitoring Unit
        1. 21.5.13.1 Pulse Width and Period Monitoring
        2. 21.5.13.2 Edge Monitoring
    6. 21.6  Application of the eCAP Module
      1. 21.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 21.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 21.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 21.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 21.7  Application of the APWM Mode
      1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 21.8  High Resolution Capture (HRCAP) Module
      1. 21.8.1 Introduction
        1. 21.8.1.1 HRCAP Related Collateral
        2. 21.8.1.2 Features
        3. 21.8.1.3 Description
      2. 21.8.2 Operational Details
        1. 21.8.2.1 HRCAP Clocking
        2. 21.8.2.2 HRCAP Initialization Sequence
        3. 21.8.2.3 HRCAP Interrupts
        4. 21.8.2.4 HRCAP Calibration
          1. 21.8.2.4.1 Applying the Scale Factor
      3. 21.8.3 Known Exceptions
    9. 21.9  Software
      1. 21.9.1 ECAP Examples
        1. 21.9.1.1 eCAP APWM Example - SINGLE_CORE
        2. 21.9.1.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 21.9.1.3 eCAP APWM Phase-shift Example - SINGLE_CORE
      2. 21.9.2 HRCAP Examples
        1. 21.9.2.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    10. 21.10 eCAP Registers
      1. 21.10.1 ECAP Base Address Table
      2. 21.10.2 ECAP_REGS Registers
      3. 21.10.3 ECAP_SIGNAL_MONITORING Registers
      4. 21.10.4 ECAP Registers to Driverlib Functions
    11. 21.11 HRCAP Registers
      1. 21.11.1 HRCAP Base Address Table
      2. 21.11.2 HRCAP_REGS Registers
      3. 21.11.3 HRCAP Registers to Driverlib Functions
  24. 22Enhanced Pulse Width Modulator (ePWM)
    1. 22.1  Introduction
      1. 22.1.1 EPWM Related Collateral
      2. 22.1.2 Submodule Overview
    2. 22.2  Configuring Device Pins
    3. 22.3  ePWM Modules Overview
    4. 22.4  Time-Base (TB) Submodule
      1. 22.4.1 Purpose of the Time-Base Submodule
      2. 22.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 22.4.3 Calculating PWM Period and Frequency
        1. 22.4.3.1 Time-Base Period Shadow Register
        2. 22.4.3.2 Time-Base Clock Synchronization
        3. 22.4.3.3 Time-Base Counter Synchronization
        4. 22.4.3.4 ePWM SYNC Selection
      4. 22.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 22.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 22.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 22.4.7 Global Load
        1. 22.4.7.1 Global Load Pulse Pre-Scalar
        2. 22.4.7.2 One-Shot Load Mode
        3. 22.4.7.3 One-Shot Sync Mode
    5. 22.5  Counter-Compare (CC) Submodule
      1. 22.5.1 Purpose of the Counter-Compare Submodule
      2. 22.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 22.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 22.5.4 Count Mode Timing Waveforms
    6. 22.6  Action-Qualifier (AQ) Submodule
      1. 22.6.1 Purpose of the Action-Qualifier Submodule
      2. 22.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 22.6.3 Action-Qualifier Event Priority
      4. 22.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 22.6.5 Configuration Requirements for Common Waveforms
    7. 22.7  XCMP Complex Waveform Generator Mode
      1. 22.7.1 XCMP Allocation to CMPA and CMPB
      2. 22.7.2 XCMP Shadow Buffers
      3. 22.7.3 XCMP Operation
    8. 22.8  Dead-Band Generator (DB) Submodule
      1. 22.8.1 Purpose of the Dead-Band Submodule
      2. 22.8.2 Dead-band Submodule Additional Operating Modes
      3. 22.8.3 Operational Highlights for the Dead-Band Submodule
    9. 22.9  PWM Chopper (PC) Submodule
      1. 22.9.1 Purpose of the PWM Chopper Submodule
      2. 22.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 22.9.3 Waveforms
        1. 22.9.3.1 One-Shot Pulse
        2. 22.9.3.2 Duty Cycle Control
    10. 22.10 Trip-Zone (TZ) Submodule
      1. 22.10.1 Purpose of the Trip-Zone Submodule
      2. 22.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 22.10.2.1 Trip-Zone Configurations
      3. 22.10.3 Generating Trip Event Interrupts
    11. 22.11 Diode Emulation (DE) Submodule
      1. 22.11.1 DEACTIVE Mode
      2. 22.11.2 Exiting DE Mode
      3. 22.11.3 Re-Entering DE Mode
      4. 22.11.4 DE Monitor
    12. 22.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 22.12.1 Minimum Dead-Band (MINDB)
      2. 22.12.2 Illegal Combo Logic (ICL)
    13. 22.13 Event-Trigger (ET) Submodule
      1. 22.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 22.14 Digital Compare (DC) Submodule
      1. 22.14.1 Purpose of the Digital Compare Submodule
      2. 22.14.2 Enhanced Trip Action Using CMPSS
      3. 22.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 22.14.4 Operation Highlights of the Digital Compare Submodule
        1. 22.14.4.1 Digital Compare Events
        2. 22.14.4.2 Event Filtering
        3. 22.14.4.3 Valley Switching
        4. 22.14.4.4 Event Detection
          1. 22.14.4.4.1 Input Signal Detection
          2. 22.14.4.4.2 MIN and MAX Detection Circuit
    15. 22.15 ePWM Crossbar (X-BAR)
    16. 22.16 Applications to Power Topologies
      1. 22.16.1  Overview of Multiple Modules
      2. 22.16.2  Key Configuration Capabilities
      3. 22.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 22.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 22.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 22.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 22.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 22.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 22.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 22.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 22.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 22.17 Register Lock Protection
    18. 22.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 22.18.1 Operational Description of HRPWM
        1. 22.18.1.1 Controlling the HRPWM Capabilities
        2. 22.18.1.2 HRPWM Source Clock
        3. 22.18.1.3 Configuring the HRPWM
        4. 22.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 22.18.1.5 Principle of Operation
          1. 22.18.1.5.1 Edge Positioning
          2. 22.18.1.5.2 Scaling Considerations
          3. 22.18.1.5.3 Duty Cycle Range Limitation
          4. 22.18.1.5.4 High-Resolution Period
            1. 22.18.1.5.4.1 High-Resolution Period Configuration
        6. 22.18.1.6 Deadband High-Resolution Operation
        7. 22.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 22.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 22.18.1.8.1 #Defines for HRPWM Header Files
          2. 22.18.1.8.2 Implementing a Simple Buck Converter
            1. 22.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 22.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 22.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 22.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 22.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 22.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 22.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 22.18.2.2 Software Usage
          1. 22.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1198
          3. 22.18.2.2.2 Declaring an Element
          4.        1200
          5. 22.18.2.2.3 Initializing With a Scale Factor Value
          6.        1202
          7. 22.18.2.2.4 SFO Function Calls
    19. 22.19 Software
      1. 22.19.1 EPWM Examples
        1. 22.19.1.1  ePWM Trip Zone - SINGLE_CORE
        2. 22.19.1.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 22.19.1.3  ePWM Synchronization - SINGLE_CORE
        4. 22.19.1.4  ePWM Digital Compare - SINGLE_CORE
        5. 22.19.1.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 22.19.1.6  ePWM Valley Switching - SINGLE_CORE
        7. 22.19.1.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 22.19.1.8  ePWM Deadband - SINGLE_CORE
        9. 22.19.1.9  ePWM DMA - SINGLE_CORE
        10. 22.19.1.10 ePWM Chopper - SINGLE_CORE
        11. 22.19.1.11 EPWM Configure Signal - SINGLE_CORE
        12. 22.19.1.12 Realization of Monoshot mode - SINGLE_CORE
        13. 22.19.1.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 22.19.1.14 ePWM XCMP Mode - SINGLE_CORE
        15. 22.19.1.15 ePWM Event Detection - SINGLE_CORE
      2. 22.19.2 HRPWM Examples
        1. 22.19.2.1 HRPWM Duty Control with SFO
        2. 22.19.2.2 HRPWM Slider
        3. 22.19.2.3 HRPWM Period Control
        4. 22.19.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 22.19.2.5 HRPWM Slider Test
        6. 22.19.2.6 HRPWM Duty Up Count
        7. 22.19.2.7 HRPWM Period Up-Down Count
    20. 22.20 ePWM Registers
      1. 22.20.1 EPWM Base Address Table
      2. 22.20.2 EPWM_REGS Registers
      3. 22.20.3 EPWM_XCMP_REGS Registers
      4. 22.20.4 DE_REGS Registers
      5. 22.20.5 MINDB_LUT_REGS Registers
      6. 22.20.6 HRPWMCAL_REGS Registers
      7. 22.20.7 Register to Driverlib Function Mapping
        1. 22.20.7.1 EPWM Registers to Driverlib Functions
        2. 22.20.7.2 HRPWM Registers to Driverlib Functions
        3. 22.20.7.3 HRPWMCAL Registers to Driverlib Functions
  25. 23Enhanced Quadrature Encoder Pulse (eQEP)
    1. 23.1  Introduction
      1. 23.1.1 EQEP Related Collateral
    2. 23.2  Configuring Device Pins
    3. 23.3  Description
      1. 23.3.1 EQEP Inputs
      2. 23.3.2 Functional Description
      3. 23.3.3 eQEP Memory Map
    4. 23.4  Quadrature Decoder Unit (QDU)
      1. 23.4.1 Position Counter Input Modes
        1. 23.4.1.1 Quadrature Count Mode
        2. 23.4.1.2 Direction-Count Mode
        3. 23.4.1.3 Up-Count Mode
        4. 23.4.1.4 Down-Count Mode
      2. 23.4.2 eQEP Input Polarity Selection
      3. 23.4.3 Position-Compare Sync Output
    5. 23.5  Position Counter and Control Unit (PCCU)
      1. 23.5.1 Position Counter Operating Modes
        1. 23.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 23.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 23.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 23.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 23.5.2 Position Counter Latch
        1. 23.5.2.1 Index Event Latch
        2. 23.5.2.2 Strobe Event Latch
      3. 23.5.3 Position Counter Initialization
      4. 23.5.4 eQEP Position-compare Unit
    6. 23.6  eQEP Edge Capture Unit
    7. 23.7  eQEP Watchdog
    8. 23.8  eQEP Unit Timer Base
    9. 23.9  QMA Module
      1. 23.9.1 Modes of Operation
        1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 23.9.2 Interrupt and Error Generation
    10. 23.10 eQEP Interrupt Structure
    11. 23.11 Software
      1. 23.11.1 EQEP Examples
        1. 23.11.1.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 23.11.1.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 23.12 eQEP Registers
      1. 23.12.1 EQEP Base Address Table
      2. 23.12.2 EQEP_REGS Registers
      3. 23.12.3 EQEP Registers to Driverlib Functions
  26. 24Sigma Delta Filter Module (SDFM)
    1. 24.1  Introduction
      1. 24.1.1 SDFM Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  Configuring Device Pins
    3. 24.3  Input Qualification
    4. 24.4  Input Control Unit
    5. 24.5  SDFM Clock Control
    6. 24.6  Sinc Filter
      1. 24.6.1 Data Rate and Latency of the Sinc Filter
    7. 24.7  Data (Primary) Filter Unit
      1. 24.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 24.7.2 Data FIFO
      3. 24.7.3 SDSYNC Event
    8. 24.8  Comparator (Secondary) Filter Unit
      1. 24.8.1 Higher Threshold (HLT) Comparators
      2. 24.8.2 Lower Threshold (LLT) Comparators
      3. 24.8.3 Digital Filter
    9. 24.9  Theoretical SDFM Filter Output
    10. 24.10 Interrupt Unit
      1. 24.10.1 SDFM (SDyERR) Interrupt Sources
      2. 24.10.2 Data Ready (DRINT) Interrupt Sources
    11. 24.11 Software
      1. 24.11.1 SDFM Examples
        1. 24.11.1.1 SDFM Filter Sync CPU
        2. 24.11.1.2 SDFM Filter Sync CLA
        3. 24.11.1.3 SDFM Filter Sync DMA
        4. 24.11.1.4 SDFM PWM Sync
        5. 24.11.1.5 SDFM Type 1 Filter FIFO
        6. 24.11.1.6 SDFM Filter Sync CLA
    12. 24.12 SDFM Registers
      1. 24.12.1 SDFM Base Address Table
      2. 24.12.2 SDFM_REGS Registers
      3. 24.12.3 SDFM Registers to Driverlib Functions
  27. 25Controller Area Network (CAN)
    1. 25.1  Introduction
      1. 25.1.1 DCAN Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
        1. 25.1.3.1 CAN Core
        2. 25.1.3.2 Message Handler
        3. 25.1.3.3 Message RAM
        4. 25.1.3.4 Registers and Message Object Access (IFx)
    2. 25.2  Functional Description
      1. 25.2.1 Configuring Device Pins
      2. 25.2.2 Address/Data Bus Bridge
    3. 25.3  Operating Modes
      1. 25.3.1 Initialization
      2. 25.3.2 CAN Message Transfer (Normal Operation)
        1. 25.3.2.1 Disabled Automatic Retransmission
        2. 25.3.2.2 Auto-Bus-On
      3. 25.3.3 Test Modes
        1. 25.3.3.1 Silent Mode
        2. 25.3.3.2 Loopback Mode
        3. 25.3.3.3 External Loopback Mode
        4. 25.3.3.4 Loopback Combined with Silent Mode
    4. 25.4  Multiple Clock Source
    5. 25.5  Interrupt Functionality
      1. 25.5.1 Message Object Interrupts
      2. 25.5.2 Status Change Interrupts
      3. 25.5.3 Error Interrupts
      4. 25.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 25.5.5 Interrupt Topologies
    6. 25.6  DMA Functionality
    7. 25.7  Parity Check Mechanism
      1. 25.7.1 Behavior on Parity Error
    8. 25.8  Debug Mode
    9. 25.9  Module Initialization
    10. 25.10 Configuration of Message Objects
      1. 25.10.1 Configuration of a Transmit Object for Data Frames
      2. 25.10.2 Configuration of a Transmit Object for Remote Frames
      3. 25.10.3 Configuration of a Single Receive Object for Data Frames
      4. 25.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 25.10.5 Configuration of a FIFO Buffer
    11. 25.11 Message Handling
      1. 25.11.1  Message Handler Overview
      2. 25.11.2  Receive/Transmit Priority
      3. 25.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 25.11.4  Updating a Transmit Object
      5. 25.11.5  Changing a Transmit Object
      6. 25.11.6  Acceptance Filtering of Received Messages
      7. 25.11.7  Reception of Data Frames
      8. 25.11.8  Reception of Remote Frames
      9. 25.11.9  Reading Received Messages
      10. 25.11.10 Requesting New Data for a Receive Object
      11. 25.11.11 Storing Received Messages in FIFO Buffers
      12. 25.11.12 Reading from a FIFO Buffer
    12. 25.12 CAN Bit Timing
      1. 25.12.1 Bit Time and Bit Rate
        1. 25.12.1.1 Synchronization Segment
        2. 25.12.1.2 Propagation Time Segment
        3. 25.12.1.3 Phase Buffer Segments and Synchronization
        4. 25.12.1.4 Oscillator Tolerance Range
      2. 25.12.2 Configuration of the CAN Bit Timing
        1. 25.12.2.1 Calculation of the Bit Timing Parameters
        2. 25.12.2.2 Example for Bit Timing at High Baudrate
        3. 25.12.2.3 Example for Bit Timing at Low Baudrate
    13. 25.13 Message Interface Register Sets
      1. 25.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 25.13.2 Message Interface Register Set 3 (IF3)
    14. 25.14 Message RAM
      1. 25.14.1 Structure of Message Objects
      2. 25.14.2 Addressing Message Objects in RAM
      3. 25.14.3 Message RAM Representation in Debug Mode
    15. 25.15 Software
      1. 25.15.1 CAN Examples
        1. 25.15.1.1  CAN Dual Core Example - C28X_DUAL
        2. 25.15.1.2  CAN External Loopback
        3. 25.15.1.3  CAN External Loopback - C28X_DUAL
        4. 25.15.1.4  CAN External Loopback with Interrupts
        5. 25.15.1.5  CAN External Loopback with Interrupts - C28X_DUAL
        6. 25.15.1.6  CAN External Loopback with DMA
        7. 25.15.1.7  CAN Transmit and Receive Configurations
        8. 25.15.1.8  CAN Error Generation Example
        9. 25.15.1.9  CAN Remote Request Loopback
        10. 25.15.1.10 CAN example that illustrates the usage of Mask registers
    16. 25.16 CAN Registers
      1. 25.16.1 CAN Base Address Table
      2. 25.16.2 CAN_REGS Registers
      3. 25.16.3 CAN Registers to Driverlib Functions
  28. 26EtherCAT® SubordinateDevice Controller (ESC)
    1. 26.1 Introduction
      1. 26.1.1  ECAT Related Collateral
      2. 26.1.2  ESC Features
      3. 26.1.3  ESC Subsystem Integrated Features
      4. 26.1.4  F28P65x ESC versus Beckhoff ET1100
      5. 26.1.5  EtherCAT IP Block Diagram
      6. 26.1.6  ESC Functional Blocks
        1. 26.1.6.1  Interface to EtherCAT MainDevice
        2. 26.1.6.2  Process Data Interface
        3. 26.1.6.3  General-Purpose Inputs and Outputs
        4. 26.1.6.4  EtherCAT Processing Unit (EPU)
        5. 26.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 26.1.6.6  Sync Manager
        7. 26.1.6.7  Monitoring
        8. 26.1.6.8  Reset Controller
        9. 26.1.6.9  PHY Management
        10. 26.1.6.10 Distributed Clock (DC)
        11. 26.1.6.11 EEPROM
        12. 26.1.6.12 Status / LEDs
      7. 26.1.7  EtherCAT Physical Layer
        1. 26.1.7.1 MII Interface
        2. 26.1.7.2 PHY Management Interface
          1. 26.1.7.2.1 PHY Address Configuration
          2. 26.1.7.2.2 PHY Reset Signal
          3. 26.1.7.2.3 PHY Clock
      8. 26.1.8  EtherCAT Protocol
      9. 26.1.9  EtherCAT State Machine (ESM)
      10. 26.1.10 More Information on EtherCAT
      11. 26.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 26.2 ESC and ESCSS Description
      1. 26.2.1  ESC RAM Parity and Memory Address Maps
        1. 26.2.1.1 ESC RAM Parity Logic
        2. 26.2.1.2 CPU1 and CPU2 ESC Memory Address Map
      2. 26.2.2  Local Host Communication
        1. 26.2.2.1 Byte Accessibility Through PDI
        2. 26.2.2.2 Software Details for Operation Across Clock Domains
      3. 26.2.3  Debug Emulation Mode Operation
      4. 26.2.4  ESC SubSystem
        1. 26.2.4.1 CPU1 Bus Interface
        2. 26.2.4.2 CPU2 Bus Interface
      5. 26.2.5  Interrupts and Interrupt Mapping
      6. 26.2.6  Power, Clocks, and Resets
        1. 26.2.6.1 Power
        2. 26.2.6.2 Clocking
        3. 26.2.6.3 Resets
          1. 26.2.6.3.1 Chip-Level Reset
          2. 26.2.6.3.2 EtherCAT Soft Resets
          3. 26.2.6.3.3 Reset Out (RESET_OUT)
      7. 26.2.7  LED Controls
      8. 26.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 26.2.9  General-Purpose Inputs and Outputs
        1. 26.2.9.1 General-Purpose Inputs
        2. 26.2.9.2 General-Purpose Output
      10. 26.2.10 Distributed Clocks – Sync and Latch
        1. 26.2.10.1 Clock Synchronization
        2. 26.2.10.2 SYNC Signals
          1. 26.2.10.2.1 Seeking Host Intervention
        3. 26.2.10.3 LATCH Signals
          1. 26.2.10.3.1 Timestamping
        4. 26.2.10.4 Device Control and Synchronization
          1. 26.2.10.4.1 Synchronization of PWM
          2. 26.2.10.4.2 ECAP SYNC Inputs
          3. 26.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 26.3 Software Initialization Sequence and Allocating Ownership
    4. 26.4 ESC Configuration Constants
    5. 26.5 EtherCAT IP Registers
      1. 26.5.1 ETHERCAT Base Address Table
      2. 26.5.2 ESCSS_REGS Registers
      3. 26.5.3 ESCSS_CONFIG_REGS Registers
      4. 26.5.4 ESC_SS Registers to Driverlib Functions
  29. 27Fast Serial Interface (FSI)
    1. 27.1 Introduction
      1. 27.1.1 FSI Related Collateral
      2. 27.1.2 FSI Features
    2. 27.2 System-level Integration
      1. 27.2.1 CPU Interface
      2. 27.2.2 Signal Description
        1. 27.2.2.1 Configuring Device Pins
      3. 27.2.3 FSI Interrupts
        1. 27.2.3.1 Transmitter Interrupts
        2. 27.2.3.2 Receiver Interrupts
        3. 27.2.3.3 Configuring Interrupts
        4. 27.2.3.4 Handling Interrupts
      4. 27.2.4 CLA Task Triggering
      5. 27.2.5 DMA Interface
      6. 27.2.6 External Frame Trigger Mux
    3. 27.3 FSI Functional Description
      1. 27.3.1  Introduction to Operation
      2. 27.3.2  FSI Transmitter Module
        1. 27.3.2.1 Initialization
        2. 27.3.2.2 FSI_TX Clocking
        3. 27.3.2.3 Transmitting Frames
          1. 27.3.2.3.1 Software Triggered Frames
          2. 27.3.2.3.2 Externally Triggered Frames
          3. 27.3.2.3.3 Ping Frame Generation
            1. 27.3.2.3.3.1 Automatic Ping Frames
            2. 27.3.2.3.3.2 Software Triggered Ping Frame
            3. 27.3.2.3.3.3 Externally Triggered Ping Frame
          4. 27.3.2.3.4 Transmitting Frames with DMA
        4. 27.3.2.4 Transmit Buffer Management
        5. 27.3.2.5 CRC Submodule
        6. 27.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 27.3.2.7 Reset
      3. 27.3.3  FSI Receiver Module
        1. 27.3.3.1  Initialization
        2. 27.3.3.2  FSI_RX Clocking
        3. 27.3.3.3  Receiving Frames
          1. 27.3.3.3.1 Receiving Frames with DMA
        4. 27.3.3.4  Ping Frame Watchdog
        5. 27.3.3.5  Frame Watchdog
        6. 27.3.3.6  Delay Line Control
        7. 27.3.3.7  Buffer Management
        8. 27.3.3.8  CRC Submodule
        9. 27.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 27.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 27.3.3.11 FSI_RX Reset
      4. 27.3.4  Frame Format
        1. 27.3.4.1 FSI Frame Phases
        2. 27.3.4.2 Frame Types
          1. 27.3.4.2.1 Ping Frames
          2. 27.3.4.2.2 Error Frames
          3. 27.3.4.2.3 Data Frames
        3. 27.3.4.3 Multi-Lane Transmission
      5. 27.3.5  Flush Sequence
      6. 27.3.6  Internal Loopback
      7. 27.3.7  CRC Generation
      8. 27.3.8  ECC Module
      9. 27.3.9  Tag Matching
      10. 27.3.10 User Data Filtering (UDATA Matching)
      11. 27.3.11 TDM Configurations
      12. 27.3.12 FSI Trigger Generation
      13. 27.3.13 FSI-SPI Compatibility Mode
        1. 27.3.13.1 Available SPI Modes
          1. 27.3.13.1.1 FSITX as SPI Controller, Transmit Only
            1. 27.3.13.1.1.1 Initialization
            2. 27.3.13.1.1.2 Operation
          2. 27.3.13.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 27.3.13.1.2.1 Initialization
            2. 27.3.13.1.2.2 Operation
          3. 27.3.13.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 27.3.13.1.3.1 Initialization
            2. 27.3.13.1.3.2 Operation
    4. 27.4 FSI Programing Guide
      1. 27.4.1 Establishing the Communication Link
        1. 27.4.1.1 Establishing the Communication Link from the Main Device
        2. 27.4.1.2 Establishing the Communication Link from the Remote Device
      2. 27.4.2 Register Protection
      3. 27.4.3 Emulation Mode
    5. 27.5 Software
      1. 27.5.1 FSI Examples
        1. 27.5.1.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 27.5.1.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 27.6 FSI Registers
      1. 27.6.1 FSI Base Address Table
      2. 27.6.2 FSI_TX_REGS Registers
      3. 27.6.3 FSI_RX_REGS Registers
      4. 27.6.4 FSI Registers to Driverlib Functions
  30. 28Inter-Integrated Circuit Module (I2C)
    1. 28.1 Introduction
      1. 28.1.1 I2C Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Features Not Supported
      4. 28.1.4 Functional Overview
      5. 28.1.5 Clock Generation
      6. 28.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 28.1.6.1 Formula for the Controller Clock Period
    2. 28.2 Configuring Device Pins
    3. 28.3 I2C Module Operational Details
      1. 28.3.1  Input and Output Voltage Levels
      2. 28.3.2  Selecting Pullup Resistors
      3. 28.3.3  Data Validity
      4. 28.3.4  Operating Modes
      5. 28.3.5  I2C Module START and STOP Conditions
      6. 28.3.6  Non-repeat Mode versus Repeat Mode
      7. 28.3.7  Serial Data Formats
        1. 28.3.7.1 7-Bit Addressing Format
        2. 28.3.7.2 10-Bit Addressing Format
        3. 28.3.7.3 Free Data Format
        4. 28.3.7.4 Using a Repeated START Condition
      8. 28.3.8  Clock Synchronization
      9. 28.3.9  Arbitration
      10. 28.3.10 Digital Loopback Mode
      11. 28.3.11 NACK Bit Generation
    4. 28.4 Interrupt Requests Generated by the I2C Module
      1. 28.4.1 Basic I2C Interrupt Requests
      2. 28.4.2 I2C FIFO Interrupts
    5. 28.5 Resetting or Disabling the I2C Module
    6. 28.6 Software
      1. 28.6.1 I2C Examples
        1. 28.6.1.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 28.6.1.2 I2C EEPROM - SINGLE_CORE
        3. 28.6.1.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 28.6.1.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 28.6.1.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 28.7 I2C Registers
      1. 28.7.1 I2C Base Address Table
      2. 28.7.2 I2C_REGS Registers
      3. 28.7.3 I2C Registers to Driverlib Functions
  31. 29Power Management Bus Module (PMBus)
    1. 29.1 Introduction
      1. 29.1.1 PMBUS Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Block Diagram
    2. 29.2 Configuring Device Pins
    3. 29.3 Target Mode Operation
      1. 29.3.1 Configuration
      2. 29.3.2 Message Handling
        1. 29.3.2.1  Quick Command
        2. 29.3.2.2  Send Byte
        3. 29.3.2.3  Receive Byte
        4. 29.3.2.4  Write Byte and Write Word
        5. 29.3.2.5  Read Byte and Read Word
        6. 29.3.2.6  Process Call
        7. 29.3.2.7  Block Write
        8. 29.3.2.8  Block Read
        9. 29.3.2.9  Block Write-Block Read Process Call
        10. 29.3.2.10 Alert Response
        11. 29.3.2.11 Extended Command
        12. 29.3.2.12 Group Command
    4. 29.4 Controller Mode Operation
      1. 29.4.1 Configuration
      2. 29.4.2 Message Handling
        1. 29.4.2.1  Quick Command
        2. 29.4.2.2  Send Byte
        3. 29.4.2.3  Receive Byte
        4. 29.4.2.4  Write Byte and Write Word
        5. 29.4.2.5  Read Byte and Read Word
        6. 29.4.2.6  Process Call
        7. 29.4.2.7  Block Write
        8. 29.4.2.8  Block Read
        9. 29.4.2.9  Block Write-Block Read Process Call
        10. 29.4.2.10 Alert Response
        11. 29.4.2.11 Extended Command
        12. 29.4.2.12 Group Command
    5. 29.5 PMBUS Registers
      1. 29.5.1 PMBUS Base Address Table
      2. 29.5.2 PMBUS_REGS Registers
      3. 29.5.3 PMBUS Registers to Driverlib Functions
  32. 30Serial Communications Interface (SCI)
    1. 30.1  Introduction
      1. 30.1.1 Features
      2. 30.1.2 SCI Related Collateral
      3. 30.1.3 Block Diagram
    2. 30.2  Architecture
    3. 30.3  SCI Module Signal Summary
    4. 30.4  Configuring Device Pins
    5. 30.5  Multiprocessor and Asynchronous Communication Modes
    6. 30.6  SCI Programmable Data Format
    7. 30.7  SCI Multiprocessor Communication
      1. 30.7.1 Recognizing the Address Byte
      2. 30.7.2 Controlling the SCI TX and RX Features
      3. 30.7.3 Receipt Sequence
    8. 30.8  Idle-Line Multiprocessor Mode
      1. 30.8.1 Idle-Line Mode Steps
      2. 30.8.2 Block Start Signal
      3. 30.8.3 Wake-Up Temporary (WUT) Flag
        1. 30.8.3.1 Sending a Block Start Signal
      4. 30.8.4 Receiver Operation
    9. 30.9  Address-Bit Multiprocessor Mode
      1. 30.9.1 Sending an Address
    10. 30.10 SCI Communication Format
      1. 30.10.1 Receiver Signals in Communication Modes
      2. 30.10.2 Transmitter Signals in Communication Modes
    11. 30.11 SCI Port Interrupts
      1. 30.11.1 Break Detect
    12. 30.12 SCI Baud Rate Calculations
    13. 30.13 SCI Enhanced Features
      1. 30.13.1 SCI FIFO Description
      2. 30.13.2 SCI Auto-Baud
      3. 30.13.3 Autobaud-Detect Sequence
    14. 30.14 Software
      1. 30.14.1 SCI Examples
        1. 30.14.1.1 Tune Baud Rate via UART Example
        2. 30.14.1.2 SCI FIFO Digital Loop Back
        3. 30.14.1.3 SCI Digital Loop Back with Interrupts
        4. 30.14.1.4 SCI Echoback
        5. 30.14.1.5 stdout redirect example
    15. 30.15 SCI Registers
      1. 30.15.1 SCI Base Address Table
      2. 30.15.2 SCI_REGS Registers
      3. 30.15.3 SCI Registers to Driverlib Functions
  33. 31Serial Peripheral Interface (SPI)
    1. 31.1 Introduction
      1. 31.1.1 Features
      2. 31.1.2 SPI Related Collateral
      3. 31.1.3 Block Diagram
    2. 31.2 System-Level Integration
      1. 31.2.1 SPI Module Signals
      2. 31.2.2 Configuring Device Pins
        1. 31.2.2.1 GPIOs Required for High-Speed Mode
      3. 31.2.3 SPI Interrupts
      4. 31.2.4 DMA Support
    3. 31.3 SPI Operation
      1. 31.3.1  Introduction to Operation
      2. 31.3.2  Controller Mode
      3. 31.3.3  Peripheral Mode
      4. 31.3.4  Data Format
        1. 31.3.4.1 Transmission of Bit from SPIRXBUF
      5. 31.3.5  Baud Rate Selection
        1. 31.3.5.1 Baud Rate Determination
        2. 31.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 31.3.6  SPI Clocking Schemes
      7. 31.3.7  SPI FIFO Description
      8. 31.3.8  SPI DMA Transfers
        1. 31.3.8.1 Transmitting Data Using SPI with DMA
        2. 31.3.8.2 Receiving Data Using SPI with DMA
      9. 31.3.9  SPI High-Speed Mode
      10. 31.3.10 SPI 3-Wire Mode Description
    4. 31.4 Programming Procedure
      1. 31.4.1 Initialization Upon Reset
      2. 31.4.2 Configuring the SPI
      3. 31.4.3 Configuring the SPI for High-Speed Mode
      4. 31.4.4 Data Transfer Example
      5. 31.4.5 SPI 3-Wire Mode Code Examples
        1. 31.4.5.1 3-Wire Controller Mode Transmit
        2.       1721
          1. 31.4.5.2.1 3-Wire Controller Mode Receive
        3.       1723
          1. 31.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1725
          1. 31.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 31.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 31.5 Software
      1. 31.5.1 SPI Examples
        1. 31.5.1.1 SPI Digital Loopback - SINGLE_CORE
        2. 31.5.1.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 31.5.1.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 31.5.1.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 31.5.1.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 31.6 SPI Registers
      1. 31.6.1 SPI Base Address Table
      2. 31.6.2 SPI_REGS Registers
      3. 31.6.3 SPI Registers to Driverlib Functions
  34. 32Universal Serial Bus (USB) Controller
    1. 32.1 Introduction
      1. 32.1.1 Features
      2. 32.1.2 USB Related Collateral
      3. 32.1.3 Block Diagram
        1. 32.1.3.1 Signal Description
        2. 32.1.3.2 VBus Recommendations
    2. 32.2 Functional Description
      1. 32.2.1 Operation as a Device
        1. 32.2.1.1 Control and Configurable Endpoints
          1. 32.2.1.1.1 IN Transactions as a Device
          2. 32.2.1.1.2 Out Transactions as a Device
          3. 32.2.1.1.3 Scheduling
          4. 32.2.1.1.4 Additional Actions
          5. 32.2.1.1.5 Device Mode Suspend
          6. 32.2.1.1.6 Start of Frame
          7. 32.2.1.1.7 USB Reset
          8. 32.2.1.1.8 Connect/Disconnect
      2. 32.2.2 Operation as a Host
        1. 32.2.2.1 Endpoint Registers
        2. 32.2.2.2 IN Transactions as a Host
        3. 32.2.2.3 OUT Transactions as a Host
        4. 32.2.2.4 Transaction Scheduling
        5. 32.2.2.5 USB Hubs
        6. 32.2.2.6 Babble
        7. 32.2.2.7 Host SUSPEND
        8. 32.2.2.8 USB RESET
        9. 32.2.2.9 Connect/Disconnect
      3. 32.2.3 DMA Operation
      4. 32.2.4 Address/Data Bus Bridge
    3. 32.3 Initialization and Configuration
      1. 32.3.1 Pin Configuration
      2. 32.3.2 Endpoint Configuration
    4. 32.4 USB Global Interrupts
    5. 32.5 Software
      1. 32.5.1 USB Examples
        1. 32.5.1.1  USB CDC serial example
        2. 32.5.1.2  USB HID Mouse Device
        3. 32.5.1.3  USB Device Keyboard
        4. 32.5.1.4  USB Generic Bulk Device
        5. 32.5.1.5  USB HID Mouse Host
        6. 32.5.1.6  USB HID Keyboard Host
        7. 32.5.1.7  USB Mass Storage Class Host
        8. 32.5.1.8  USB Dual Detect
        9. 32.5.1.9  USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
        10. 32.5.1.10 USB HUB Host example
    6. 32.6 USB Registers
      1. 32.6.1 USB Base Address Table
      2. 32.6.2 USB_REGS Registers
      3. 32.6.3 USB Registers to Driverlib Functions
  35. 33Advanced Encryption Standard (AES) Accelerator
    1. 33.1 Introduction
      1. 33.1.1 AES Block Diagram
        1. 33.1.1.1 Interfaces
        2. 33.1.1.2 AES Subsystem
        3. 33.1.1.3 AES Wide-Bus Engine
      2. 33.1.2 AES Algorithm
    2. 33.2 AES Operating Modes
      1. 33.2.1  GCM Operation
      2. 33.2.2  CCM Operation
      3. 33.2.3  XTS Operation
      4. 33.2.4  ECB Feedback Mode
      5. 33.2.5  CBC Feedback Mode
      6. 33.2.6  CTR and ICM Feedback Modes
      7. 33.2.7  CFB Mode
      8. 33.2.8  F8 Mode
      9. 33.2.9  F9 Operation
      10. 33.2.10 CBC-MAC Operation
    3. 33.3 Extended and Combined Modes of Operations
      1. 33.3.1 GCM Protocol Operation
      2. 33.3.2 CCM Protocol Operation
      3. 33.3.3 Hardware Requests
    4. 33.4 AES Module Programming Guide
      1. 33.4.1 AES Low-Level Programming Models
        1. 33.4.1.1 Global Initialization
        2. 33.4.1.2 AES Operating Modes Configuration
        3. 33.4.1.3 AES Mode Configurations
        4. 33.4.1.4 AES Events Servicing
    5. 33.5 Software
      1. 33.5.1 AES Examples
        1. 33.5.1.1 AES ECB Encryption Example
        2. 33.5.1.2 AES ECB De-cryption Example
        3. 33.5.1.3 AES GCM Encryption Example
        4. 33.5.1.4 AES GCM Decryption Example
    6. 33.6 AES Registers
      1. 33.6.1 AES Base Address Table
      2. 33.6.2 AES_REGS Registers
      3. 33.6.3 AES_SS_REGS Registers
      4. 33.6.4 Register to Driverlib Function Mapping
        1. 33.6.4.1 AES Registers to Driverlib Functions
        2. 33.6.4.2 AES_SS Registers to Driverlib Functions
  36. 34Embedded Pattern Generator (EPG)
    1. 34.1 Introduction
      1. 34.1.1 Features
      2. 34.1.2 EPG Block Diagram
      3. 34.1.3 EPG Related Collateral
    2. 34.2 Clock Generator Modules
      1. 34.2.1 DCLK (50% duty cycle clock)
      2. 34.2.2 Clock Stop
    3. 34.3 Signal Generator Module
    4. 34.4 EPG Peripheral Signal Mux Selection
    5. 34.5 Application Software Notes
    6. 34.6 EPG Example Use Cases
      1. 34.6.1 EPG Example: Synchronous Clocks with Offset
        1. 34.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 34.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 34.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 34.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 34.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 34.6.4 EPG Example: Clock and Data Pair
        1. 34.6.4.1 Clock and Data Pair Register Configuration
      5. 34.6.5 EPG Example: Clock and Skewed Data Pair
        1. 34.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 34.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 34.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 34.7 EPG Interrupt
    8. 34.8 Software
      1. 34.8.1 EPG Examples
        1. 34.8.1.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 34.8.1.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 34.8.1.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 34.8.1.4 EPG Generate Serial Data - SINGLE_CORE
        5. 34.8.1.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 34.9 EPG Registers
      1. 34.9.1 EPG Base Address Table
      2. 34.9.2 EPG_REGS Registers
      3. 34.9.3 EPG_MUX_REGS Registers
      4. 34.9.4 EPG Registers to Driverlib Functions
  37. 35Modular Controller Area Network (MCAN)
    1. 35.1 MCAN Introduction
      1. 35.1.1 MCAN Related Collateral
      2. 35.1.2 MCAN Features
    2. 35.2 MCAN Environment
    3. 35.3 CAN Network Basics
    4. 35.4 MCAN Integration
    5. 35.5 MCAN Functional Description
      1. 35.5.1  Module Clocking Requirements
      2. 35.5.2  Interrupt Requests
      3. 35.5.3  Operating Modes
        1. 35.5.3.1 Software Initialization
        2. 35.5.3.2 Normal Operation
        3. 35.5.3.3 CAN FD Operation
      4. 35.5.4  Transmitter Delay Compensation
        1. 35.5.4.1 Description
        2. 35.5.4.2 Transmitter Delay Compensation Measurement
      5. 35.5.5  Restricted Operation Mode
      6. 35.5.6  Bus Monitoring Mode
      7. 35.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 35.5.7.1 Frame Transmission in DAR Mode
      8. 35.5.8  Clock Stop Mode
        1. 35.5.8.1 Suspend Mode
        2. 35.5.8.2 Wakeup Request
      9. 35.5.9  Test Modes
        1. 35.5.9.1 External Loop Back Mode
        2. 35.5.9.2 Internal Loop Back Mode
      10. 35.5.10 Timestamp Generation
        1. 35.5.10.1 External Timestamp Counter
      11. 35.5.11 Timeout Counter
      12. 35.5.12 Safety
        1. 35.5.12.1 ECC Wrapper
        2. 35.5.12.2 ECC Aggregator
          1. 35.5.12.2.1 ECC Aggregator Overview
          2. 35.5.12.2.2 ECC Aggregator Registers
        3. 35.5.12.3 Reads to ECC Control and Status Registers
        4. 35.5.12.4 ECC Interrupts
      13. 35.5.13 Rx Handling
        1. 35.5.13.1 Acceptance Filtering
          1. 35.5.13.1.1 Range Filter
          2. 35.5.13.1.2 Filter for Specific IDs
          3. 35.5.13.1.3 Classic Bit Mask Filter
          4. 35.5.13.1.4 Standard Message ID Filtering
          5. 35.5.13.1.5 Extended Message ID Filtering
        2. 35.5.13.2 Rx FIFOs
          1. 35.5.13.2.1 Rx FIFO Blocking Mode
          2. 35.5.13.2.2 Rx FIFO Overwrite Mode
        3. 35.5.13.3 Dedicated Rx Buffers
          1. 35.5.13.3.1 Rx Buffer Handling
      14. 35.5.14 Tx Handling
        1. 35.5.14.1 Transmit Pause
        2. 35.5.14.2 Dedicated Tx Buffers
        3. 35.5.14.3 Tx FIFO
        4. 35.5.14.4 Tx Queue
        5. 35.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 35.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 35.5.14.7 Transmit Cancellation
        8. 35.5.14.8 Tx Event Handling
      15. 35.5.15 FIFO Acknowledge Handling
      16. 35.5.16 Message RAM
        1. 35.5.16.1 Message RAM Configuration
        2. 35.5.16.2 Rx Buffer and FIFO Element
        3. 35.5.16.3 Tx Buffer Element
        4. 35.5.16.4 Tx Event FIFO Element
        5. 35.5.16.5 Standard Message ID Filter Element
        6. 35.5.16.6 Extended Message ID Filter Element
    6. 35.6 Software
      1. 35.6.1 MCAN Examples
        1. 35.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 35.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 35.7 MCAN Registers
      1. 35.7.1 MCAN Base Address Table
      2. 35.7.2 MCANSS_REGS Registers
      3. 35.7.3 MCAN_REGS Registers
      4. 35.7.4 MCAN_ERROR_REGS Registers
      5. 35.7.5 MCAN Registers to Driverlib Functions
  38. 36Universal Asynchronous Receiver/Transmitter (UART)
    1. 36.1 Introduction
      1. 36.1.1 Features
      2. 36.1.2 Block Diagram
    2. 36.2 Functional Description
      1. 36.2.1 Transmit and Receive Logic
      2. 36.2.2 Baud-Rate Generation
      3. 36.2.3 Data Transmission
      4. 36.2.4 Serial IR (SIR)
      5. 36.2.5 9-Bit UART Mode
      6. 36.2.6 FIFO Operation
      7. 36.2.7 Interrupts
      8. 36.2.8 Loopback Operation
      9. 36.2.9 DMA Operation
        1. 36.2.9.1 Receiving Data Using UART with DMA
        2. 36.2.9.2 Transmitting Data Using UART with DMA
    3. 36.3 Initialization and Configuration
    4. 36.4 Software
      1. 36.4.1 UART Examples
        1. 36.4.1.1 UART Loopback - SINGLE_CORE
        2. 36.4.1.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 36.4.1.3 UART Loopback with DMA - SINGLE_CORE
    5. 36.5 UART Registers
      1. 36.5.1 UART Base Address Table
      2. 36.5.2 UART_REGS Registers
      3. 36.5.3 UART_REGS_WRITE Registers
      4. 36.5.4 UART Registers to Driverlib Functions
  39. 37Local Interconnect Network (LIN)
    1. 37.1 LIN Overview
      1. 37.1.1 SCI Features
      2. 37.1.2 LIN Features
      3. 37.1.3 LIN Related Collateral
      4. 37.1.4 Block Diagram
    2. 37.2 Serial Communications Interface Module
      1. 37.2.1 SCI Communication Formats
        1. 37.2.1.1 SCI Frame Formats
        2. 37.2.1.2 SCI Asynchronous Timing Mode
        3. 37.2.1.3 SCI Baud Rate
          1. 37.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 37.2.1.4 SCI Multiprocessor Communication Modes
          1. 37.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 37.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 37.2.1.5 SCI Multibuffered Mode
      2. 37.2.2 SCI Interrupts
        1. 37.2.2.1 Transmit Interrupt
        2. 37.2.2.2 Receive Interrupt
        3. 37.2.2.3 WakeUp Interrupt
        4. 37.2.2.4 Error Interrupts
      3. 37.2.3 SCI DMA Interface
        1. 37.2.3.1 Receive DMA Requests
        2. 37.2.3.2 Transmit DMA Requests
      4. 37.2.4 SCI Configurations
        1. 37.2.4.1 Receiving Data
          1. 37.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 37.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 37.2.4.2 Transmitting Data
          1. 37.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 37.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 37.2.5 SCI Low-Power Mode
        1. 37.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 37.3 Local Interconnect Network Module
      1. 37.3.1 LIN Communication Formats
        1. 37.3.1.1  LIN Standards
        2. 37.3.1.2  Message Frame
          1. 37.3.1.2.1 Message Header
          2. 37.3.1.2.2 Response
        3. 37.3.1.3  Synchronizer
        4. 37.3.1.4  Baud Rate
          1. 37.3.1.4.1 Fractional Divider
          2. 37.3.1.4.2 Superfractional Divider
            1. 37.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 37.3.1.5  Header Generation
          1. 37.3.1.5.1 Event Triggered Frame Handling
          2. 37.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 37.3.1.6  Extended Frames Handling
        7. 37.3.1.7  Timeout Control
          1. 37.3.1.7.1 No-Response Error (NRE)
          2. 37.3.1.7.2 Bus Idle Detection
          3. 37.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 37.3.1.8  TXRX Error Detector (TED)
          1. 37.3.1.8.1 Bit Errors
          2. 37.3.1.8.2 Physical Bus Errors
          3. 37.3.1.8.3 ID Parity Errors
          4. 37.3.1.8.4 Checksum Errors
        9. 37.3.1.9  Message Filtering and Validation
        10. 37.3.1.10 Receive Buffers
        11. 37.3.1.11 Transmit Buffers
      2. 37.3.2 LIN Interrupts
      3. 37.3.3 Servicing LIN Interrupts
      4. 37.3.4 LIN DMA Interface
        1. 37.3.4.1 LIN Receive DMA Requests
        2. 37.3.4.2 LIN Transmit DMA Requests
      5. 37.3.5 LIN Configurations
        1. 37.3.5.1 Receiving Data
          1. 37.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 37.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 37.3.5.2 Transmitting Data
          1. 37.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 37.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 37.4 Low-Power Mode
      1. 37.4.1 Entering Sleep Mode
      2. 37.4.2 Wakeup
      3. 37.4.3 Wakeup Timeouts
    5. 37.5 Emulation Mode
    6. 37.6 Software
      1. 37.6.1 LIN Examples
        1. 37.6.1.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 37.6.1.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 37.6.1.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 37.6.1.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 37.6.1.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 37.7 SCI/LIN Registers
      1. 37.7.1 LIN Base Address Table
      2. 37.7.2 LIN_REGS Registers
      3. 37.7.3 LIN Registers to Driverlib Functions
  40. 38Lockstep Compare Module (LCM)
    1. 38.1 Introduction
      1. 38.1.1 Features
      2. 38.1.2 Block Diagram
    2. 38.2 Enabling LCM Comparators
    3. 38.3 Disabling LCM Redundant Module
    4. 38.4 LCM Error Handling
    5. 38.5 LCM Error Flags
    6. 38.6 Debug Mode with LCM
    7. 38.7 Register Parity Error Protection
    8. 38.8 Functional Logic
      1. 38.8.1 Comparator Logic
      2. 38.8.2 Self-Test Logic
        1. 38.8.2.1 Match Test Mode
        2. 38.8.2.2 Mismatch Test Mode
      3. 38.8.3 Error Injection Tests
        1. 38.8.3.1 Comparator Error Force Test
        2. 38.8.3.2 Register Parity Error Test
    9. 38.9 LCM Registers
      1. 38.9.1 LCM Base Address Table
      2. 38.9.2 LCM_REGS Registers
      3. 38.9.3 LCM Registers to Driverlib Functions
  41. 39Revision History

14.11.2 GPIO_CTRL_REGS Registers

Table 14-12 lists the memory-mapped registers for the GPIO_CTRL_REGS registers. All register offset addresses not listed in Table 14-12 should be considered as reserved locations and the register contents should not be modified.

Table 14-12 GPIO_CTRL_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hGPACTRLGPIO A Qualification Sampling Period Control (GPIO0 to 31)EALLOWGo
2hGPAQSEL1GPIO A Qualifier Select 1 Register (GPIO0 to 15)EALLOWGo
4hGPAQSEL2GPIO A Qualifier Select 2 Register (GPIO16 to 31)EALLOWGo
6hGPAMUX1GPIO A Mux 1 Register (GPIO0 to 15)EALLOWGo
8hGPAMUX2GPIO A Mux 2 Register (GPIO16 to 31)EALLOWGo
AhGPADIRGPIO A Direction Register (GPIO0 to 31)EALLOWGo
ChGPAPUDGPIO A Pull Up Disable Register (GPIO0 to 31)EALLOWGo
10hGPAINVGPIO A Input Polarity Invert Registers (GPIO0 to 31)EALLOWGo
12hGPAODRGPIO A Open Drain Output Register (GPIO0 to GPIO31)EALLOWGo
20hGPAGMUX1GPIO A Peripheral Group Mux (GPIO0 to 15)EALLOWGo
22hGPAGMUX2GPIO A Peripheral Group Mux (GPIO16 to 31)EALLOWGo
28hGPACSEL1GPIO A Core Select Register (GPIO0 to 7)EALLOWGo
2AhGPACSEL2GPIO A Core Select Register (GPIO8 to 15)EALLOWGo
2ChGPACSEL3GPIO A Core Select Register (GPIO16 to 23)EALLOWGo
2EhGPACSEL4GPIO A Core Select Register (GPIO24 to 31)EALLOWGo
3ChGPALOCKGPIO A Lock Configuration Register (GPIO0 to 31)EALLOWGo
3EhGPACRGPIO A Lock Commit Register (GPIO0 to 31)EALLOWGo
40hGPBCTRLGPIO B Qualification Sampling Period Control (GPIO32 to 63)EALLOWGo
42hGPBQSEL1GPIO B Qualifier Select 1 Register (GPIO32 to 47)EALLOWGo
44hGPBQSEL2GPIO B Qualifier Select 2 Register (GPIO48 to 63)EALLOWGo
46hGPBMUX1GPIO B Mux 1 Register (GPIO32 to 47)EALLOWGo
48hGPBMUX2GPIO B Mux 2 Register (GPIO48 to 63)EALLOWGo
4AhGPBDIRGPIO B Direction Register (GPIO32 to 63)EALLOWGo
4ChGPBPUDGPIO B Pull Up Disable Register (GPIO32 to 63)EALLOWGo
50hGPBINVGPIO B Input Polarity Invert Registers (GPIO32 to 63)EALLOWGo
52hGPBODRGPIO B Open Drain Output Register (GPIO32 to GPIO63)EALLOWGo
54hGPBAMSELGPIO B Analog Mode Select register (GPIO32 to GPIO63)EALLOWGo
60hGPBGMUX1GPIO B Peripheral Group Mux (GPIO32 to 47)EALLOWGo
62hGPBGMUX2GPIO B Peripheral Group Mux (GPIO48 to 63)EALLOWGo
68hGPBCSEL1GPIO B Core Select Register (GPIO32 to 39)EALLOWGo
6AhGPBCSEL2GPIO B Core Select Register (GPIO40 to 47)EALLOWGo
6ChGPBCSEL3GPIO B Core Select Register (GPIO48 to 55)EALLOWGo
6EhGPBCSEL4GPIO B Core Select Register (GPIO56 to 63)EALLOWGo
7ChGPBLOCKGPIO B Lock Configuration Register (GPIO32 to 63)EALLOWGo
7EhGPBCRGPIO B Lock Commit Register (GPIO32 to 63)EALLOWGo
80hGPCCTRLGPIO C Qualification Sampling Period Control (GPIO64 to 95)EALLOWGo
82hGPCQSEL1GPIO C Qualifier Select 1 Register (GPIO64 to 79)EALLOWGo
84hGPCQSEL2GPIO C Qualifier Select 2 Register (GPIO80 to 95)EALLOWGo
86hGPCMUX1GPIO C Mux 1 Register (GPIO64 to 79)EALLOWGo
88hGPCMUX2GPIO C Mux 2 Register (GPIO80 to 95)EALLOWGo
8AhGPCDIRGPIO C Direction Register (GPIO64 to 95)EALLOWGo
8ChGPCPUDGPIO C Pull Up Disable Register (GPIO64 to 95)EALLOWGo
90hGPCINVGPIO C Input Polarity Invert Registers (GPIO64 to 95)EALLOWGo
92hGPCODRGPIO C Open Drain Output Register (GPIO64 to GPIO95)EALLOWGo
A0hGPCGMUX1GPIO C Peripheral Group Mux (GPIO64 to 79)EALLOWGo
A2hGPCGMUX2GPIO C Peripheral Group Mux (GPIO80 to 95)EALLOWGo
A8hGPCCSEL1GPIO C Core Select Register (GPIO64 to 71)EALLOWGo
AAhGPCCSEL2GPIO C Core Select Register (GPIO72 to 79)EALLOWGo
AChGPCCSEL3GPIO C Core Select Register (GPIO80 to 87)EALLOWGo
AEhGPCCSEL4GPIO C Core Select Register (GPIO88 to 95)EALLOWGo
BChGPCLOCKGPIO C Lock Configuration Register (GPIO64 to 95)EALLOWGo
BEhGPCCRGPIO C Lock Commit Register (GPIO64 to 95)EALLOWGo
C0hGPDCTRLGPIO D Qualification Sampling Period Control (GPIO96 to 127)EALLOWGo
C2hGPDQSEL1GPIO D Qualifier Select 1 Register (GPIO96 to 111)EALLOWGo
C4hGPDQSEL2GPIO D Qualifier Select 2 Register (GPIO112 to 127)EALLOWGo
C6hGPDMUX1GPIO D Mux 1 Register (GPIO96 to 111)EALLOWGo
C8hGPDMUX2GPIO D Mux 2 Register (GPIO112 to 127)EALLOWGo
CAhGPDDIRGPIO D Direction Register (GPIO96 to 127)EALLOWGo
CChGPDPUDGPIO D Pull Up Disable Register (GPIO96 to 127)EALLOWGo
D0hGPDINVGPIO D Input Polarity Invert Registers (GPIO96 to 127)EALLOWGo
D2hGPDODRGPIO D Open Drain Output Register (GPIO96 to GPIO127)EALLOWGo
E0hGPDGMUX1GPIO D Peripheral Group Mux (GPIO96 to 111)EALLOWGo
E2hGPDGMUX2GPIO D Peripheral Group Mux (GPIO112 to 127)EALLOWGo
E8hGPDCSEL1GPIO D Core Select Register (GPIO96 to 103)EALLOWGo
EAhGPDCSEL2GPIO D Core Select Register (GPIO104 to 111)EALLOWGo
EChGPDCSEL3GPIO D Core Select Register (GPIO112 to 119)EALLOWGo
EEhGPDCSEL4GPIO D Core Select Register (GPIO120 to 127)EALLOWGo
FChGPDLOCKGPIO D Lock Configuration Register (GPIO96 to 127)EALLOWGo
FEhGPDCRGPIO D Lock Commit Register (GPIO96 to 127)EALLOWGo
100hGPECTRLGPIO E Qualification Sampling Period Control (GPIO128 to 159)EALLOWGo
102hGPEQSEL1GPIO E Qualifier Select 1 Register (GPIO128 to 143)EALLOWGo
104hGPEQSEL2GPIO E Qualifier Select 2 Register (GPIO144 to 159)EALLOWGo
106hGPEMUX1GPIO E Mux 1 Register (GPIO128 to 143)EALLOWGo
108hGPEMUX2GPIO E Mux 2 Register (GPIO144 to 159)EALLOWGo
10AhGPEDIRGPIO E Direction Register (GPIO128 to 159)EALLOWGo
10ChGPEPUDGPIO E Pull Up Disable Register (GPIO128 to 159)EALLOWGo
110hGPEINVGPIO E Input Polarity Invert Registers (GPIO128 to 159)EALLOWGo
112hGPEODRGPIO E Open Drain Output Register (GPIO128 to GPIO159)EALLOWGo
120hGPEGMUX1GPIO E Peripheral Group Mux (GPIO128 to 143)EALLOWGo
122hGPEGMUX2GPIO E Peripheral Group Mux (GPIO144 to 159)EALLOWGo
128hGPECSEL1GPIO E Core Select Register (GPIO128 to 135)EALLOWGo
12AhGPECSEL2GPIO E Core Select Register (GPIO136 to 143)EALLOWGo
12ChGPECSEL3GPIO E Core Select Register (GPIO144 to 151)EALLOWGo
12EhGPECSEL4GPIO E Core Select Register (GPIO152 to 159)EALLOWGo
13ChGPELOCKGPIO E Lock Configuration Register (GPIO128 to 159)EALLOWGo
13EhGPECRGPIO E Lock Commit Register (GPIO128 to 159)EALLOWGo
140hGPFCTRLGPIO F Qualification Sampling Period Control (GPIO160 to 191)EALLOWGo
142hGPFQSEL1GPIO F Qualifier Select 1 Register (GPIO160 to 168)EALLOWGo
144hGPFQSEL2GPIO F Qualifier Select 2 Register (GPIO176 to 191)EALLOWGo
146hGPFMUX1GPIO F Mux 1 Register (GPIO160 to 175)EALLOWGo
148hGPFMUX2GPIO F Mux 2 Register (GPIO176 to 191)EALLOWGo
14AhGPFDIRGPIO F Direction Register (GPIO160 to 191)EALLOWGo
14ChGPFPUDGPIO F Pull Up Disable Register (GPIO160 to 191)EALLOWGo
150hGPFINVGPIO F Input Polarity Invert Registers (GPIO160 to 191)EALLOWGo
152hGPFODRGPIO F Open Drain Output Register (GPIO160 to GPIO191)EALLOWGo
160hGPFGMUX1GPIO F Peripheral Group Mux (GPIO160 to 175)EALLOWGo
162hGPFGMUX2GPIO F Peripheral Group Mux (GPIO176 to 191)EALLOWGo
168hGPFCSEL1GPIO F Core Select Register (GPIO160 to 167)EALLOWGo
16AhGPFCSEL2GPIO F Core Select Register (GPIO168 to 175)EALLOWGo
16ChGPFCSEL3GPIO F Core Select Register (GPIO176 to 183)EALLOWGo
16EhGPFCSEL4GPIO F Core Select Register (GPIO184 to 191)EALLOWGo
17ChGPFLOCKGPIO F Lock Configuration Register (GPIO160 to 191)EALLOWGo
17EhGPFCRGPIO F Lock Commit Register (GPIO160 to 191)EALLOWGo
180hGPGCTRLGPIO G Qualification Sampling Period Control (GPIO192 to 223)EALLOWGo
182hGPGQSEL1GPIO G Qualifier Select 1 Register (GPIO192 to 207)EALLOWGo
184hGPGQSEL2GPIO G Qualifier Select 2 Register (GPIO208 to 223)EALLOWGo
186hGPGMUX1GPIO G Mux 1 Register (GPIO192 to 207)EALLOWGo
188hGPGMUX2GPIO G Mux 2 Register (GPIO208 to 223)EALLOWGo
18AhGPGDIRGPIO G Direction Register (GPIO192 to 223)EALLOWGo
18ChGPGPUDGPIO G Pull Up Disable Register (GPIO192 to 223)EALLOWGo
190hGPGINVGPIO G Input Polarity Invert Registers (GPIO192 to 223)EALLOWGo
192hGPGODRGPIO G Open Drain Output Register (GPIO192 to 223)EALLOWGo
194hGPGAMSELGPIO G Analog Mode Select register (GPIO192 to 223)EALLOWGo
1A0hGPGGMUX1GPIO G Peripheral Group Mux (GPIO192 to 207)EALLOWGo
1A2hGPGGMUX2GPIO G Peripheral Group Mux (GPIO208 to 223)EALLOWGo
1A8hGPGCSEL1GPIO G Core Select Register (GPIO192 to 199)EALLOWGo
1AAhGPGCSEL2GPIO G Core Select Register (GPIO200 to 207)EALLOWGo
1AChGPGCSEL3GPIO G Core Select Register (GPIO208 to 215)EALLOWGo
1AEhGPGCSEL4GPIO G Core Select Register (GPIO216 to 223)EALLOWGo
1BChGPGLOCKGPIO G Lock Configuration Register (GPIO192 to 223)EALLOWGo
1BEhGPGCRGPIO G Lock Commit Register (GPIO192 to 223)EALLOWGo
1C0hGPHCTRLGPIO H Qualification Sampling Period Control (GPIO224 to 255)EALLOWGo
1C2hGPHQSEL1GPIO H Qualifier Select 1 Register (GPIO224 to 239)EALLOWGo
1C4hGPHQSEL2GPIO H Qualifier Select 2 Register (GPIO240 to 255)EALLOWGo
1C6hGPHMUX1GPIO H Mux 1 Register (GPIO224 to 239)EALLOWGo
1C8hGPHMUX2GPIO H Mux 2 Register (GPIO240 to 255)EALLOWGo
1CAhGPHDIRGPIO H Direction Register (GPIO224 to 255)EALLOWGo
1CChGPHPUDGPIO H Pull Up Disable Register (GPIO224 to 255)EALLOWGo
1D0hGPHINVGPIO H Input Polarity Invert Registers (GPIO224 to 255)EALLOWGo
1D2hGPHODRGPIO H Open Drain Output Register (GPIO224 to GPIO255)EALLOWGo
1D4hGPHAMSELGPIO H Analog Mode Select register (GPIO224 to GPIO255)EALLOWGo
1E0hGPHGMUX1GPIO H Peripheral Group Mux (GPIO224 to 239)EALLOWGo
1E2hGPHGMUX2GPIO H Peripheral Group Mux (GPIO240 to 255)EALLOWGo
1E8hGPHCSEL1GPIO H Core Select Register (GPIO224 to 231)EALLOWGo
1EAhGPHCSEL2GPIO H Core Select Register (GPIO232 to 239)EALLOWGo
1EChGPHCSEL3GPIO H Core Select Register (GPIO240 to 247)EALLOWGo
1EEhGPHCSEL4GPIO H Core Select Register (GPIO248 to 255)EALLOWGo
1FChGPHLOCKGPIO H Lock Configuration Register (GPIO224 to 255)EALLOWGo
1FEhGPHCRGPIO H Lock Commit Register (GPIO224 to 255)EALLOWGo

Complex bit access types are encoded to fit into small table cells. Table 14-13 shows the codes that are used for access types in this section.

Table 14-13 GPIO_CTRL_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

14.11.2.1 GPACTRL Register (Offset = 0h) [Reset = 00000000h]

GPACTRL is shown in Figure 14-5 and described in Table 14-14.

Return to the Summary Table.

GPIO A Qualification Sampling Period Control (GPIO0 to 31)

Figure 14-5 GPACTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-14 GPACTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO24 to GPIO31:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO16 to GPIO23:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO8 to GPIO15:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO0 to GPIO7:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.2 GPAQSEL1 Register (Offset = 2h) [Reset = 00000000h]

GPAQSEL1 is shown in Figure 14-6 and described in Table 14-15.

Return to the Summary Table.

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-6 GPAQSEL1 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-15 GPAQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO15R/W0hSelect input qualification type for GPIO15:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO14R/W0hSelect input qualification type for GPIO14:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO13R/W0hSelect input qualification type for GPIO13:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO12R/W0hSelect input qualification type for GPIO12:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO11R/W0hSelect input qualification type for GPIO11:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO10R/W0hSelect input qualification type for GPIO10:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO9R/W0hSelect input qualification type for GPIO9:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO8R/W0hSelect input qualification type for GPIO8:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO7R/W0hSelect input qualification type for GPIO7:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO6R/W0hSelect input qualification type for GPIO6:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO5R/W0hSelect input qualification type for GPIO5:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO4R/W0hSelect input qualification type for GPIO4:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO3R/W0hSelect input qualification type for GPIO3:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO2R/W0hSelect input qualification type for GPIO2:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO1R/W0hSelect input qualification type for GPIO1:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO0R/W0hSelect input qualification type for GPIO0:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.3 GPAQSEL2 Register (Offset = 4h) [Reset = 00000000h]

GPAQSEL2 is shown in Figure 14-7 and described in Table 14-16.

Return to the Summary Table.

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-7 GPAQSEL2 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-16 GPAQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO31R/W0hSelect input qualification type for GPIO31:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO30R/W0hSelect input qualification type for GPIO30:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO29R/W0hSelect input qualification type for GPIO29:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO28R/W0hSelect input qualification type for GPIO28:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO27R/W0hSelect input qualification type for GPIO27:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO26R/W0hSelect input qualification type for GPIO26:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO25R/W0hSelect input qualification type for GPIO25:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO24R/W0hSelect input qualification type for GPIO24:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO23R/W0hSelect input qualification type for GPIO23:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO22R/W0hSelect input qualification type for GPIO22:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO21R/W0hSelect input qualification type for GPIO21:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO20R/W0hSelect input qualification type for GPIO20:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO19R/W0hSelect input qualification type for GPIO19:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO18R/W0hSelect input qualification type for GPIO18:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO17R/W0hSelect input qualification type for GPIO17:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO16R/W0hSelect input qualification type for GPIO16:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.4 GPAMUX1 Register (Offset = 6h) [Reset = 00000000h]

GPAMUX1 is shown in Figure 14-8 and described in Table 14-17.

Return to the Summary Table.

GPIO A Mux 1 Register (GPIO0 to 15)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-8 GPAMUX1 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-17 GPAMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO15R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO14R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO13R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO12R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO11R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO10R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO9R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO8R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO7R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO6R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO5R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO4R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO3R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO2R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO1R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO0R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.5 GPAMUX2 Register (Offset = 8h) [Reset = 00000000h]

GPAMUX2 is shown in Figure 14-9 and described in Table 14-18.

Return to the Summary Table.

GPIO A Mux 2 Register (GPIO16 to 31)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-9 GPAMUX2 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-18 GPAMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO31R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO30R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO29R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO28R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO27R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO26R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO25R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO24R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO23R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO22R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO21R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO20R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO19R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO18R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO17R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO16R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.6 GPADIR Register (Offset = Ah) [Reset = 00000000h]

GPADIR is shown in Figure 14-10 and described in Table 14-19.

Return to the Summary Table.

GPIO A Direction Register (GPIO0 to 31)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-10 GPADIR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-19 GPADIR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

30GPIO30R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

29GPIO29R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

28GPIO28R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

27GPIO27R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

26GPIO26R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

25GPIO25R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

24GPIO24R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

23GPIO23R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

22GPIO22R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

21GPIO21R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

20GPIO20R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

19GPIO19R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

18GPIO18R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO17R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16GPIO16R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

15GPIO15R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14GPIO14R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO13R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12GPIO12R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

11GPIO11R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

10GPIO10R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

9GPIO9R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

8GPIO8R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO7R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO6R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO5R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO4R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO3R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO2R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO1R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO0R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.7 GPAPUD Register (Offset = Ch) [Reset = FFFFFFFFh]

GPAPUD is shown in Figure 14-11 and described in Table 14-20.

Return to the Summary Table.

GPIO A Pull Up Disable Register (GPIO0 to 31)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-11 GPAPUD Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-20 GPAPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO30R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO29R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO28R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO27R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO26R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO25R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO24R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO23R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO22R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO21R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO20R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO19R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO18R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO17R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO16R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO15R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO14R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO13R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO12R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO11R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO10R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO9R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO8R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO7R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO6R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO5R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO4R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO3R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO2R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO1R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO0R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14.11.2.8 GPAINV Register (Offset = 10h) [Reset = 00000000h]

GPAINV is shown in Figure 14-12 and described in Table 14-21.

Return to the Summary Table.

GPIO A Input Polarity Invert Registers (GPIO0 to 31)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-12 GPAINV Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-21 GPAINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO30R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO29R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO28R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO27R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO26R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO25R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO24R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO23R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO22R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO21R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO20R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO19R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO18R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO17R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO16R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO15R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO14R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO13R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO12R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO11R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO10R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO9R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO8R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO7R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO6R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO5R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO4R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO3R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO2R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO1R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO0R/W0hInput inversion control for this pin

Reset type: SYSRSn

14.11.2.9 GPAODR Register (Offset = 12h) [Reset = 00000000h]

GPAODR is shown in Figure 14-13 and described in Table 14-22.

Return to the Summary Table.

GPIO A Open Drain Output Register (GPIO0 to GPIO31)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-13 GPAODR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-22 GPAODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

30GPIO30R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

29GPIO29R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

28GPIO28R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

27GPIO27R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

26GPIO26R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

25GPIO25R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

24GPIO24R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

23GPIO23R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

22GPIO22R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

21GPIO21R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

20GPIO20R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

19GPIO19R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

18GPIO18R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO17R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16GPIO16R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

15GPIO15R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14GPIO14R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO13R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12GPIO12R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

11GPIO11R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

10GPIO10R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

9GPIO9R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

8GPIO8R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO7R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO6R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO5R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO4R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO3R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO2R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO1R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO0R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.10 GPAGMUX1 Register (Offset = 20h) [Reset = 00000000h]

GPAGMUX1 is shown in Figure 14-14 and described in Table 14-23.

Return to the Summary Table.

GPIO A Peripheral Group Mux (GPIO0 to 15)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-14 GPAGMUX1 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-23 GPAGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO15R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO14R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO13R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO12R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO11R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO10R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO9R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO8R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO7R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO6R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO5R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO4R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO3R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO2R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO1R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO0R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.11 GPAGMUX2 Register (Offset = 22h) [Reset = 00000000h]

GPAGMUX2 is shown in Figure 14-15 and described in Table 14-24.

Return to the Summary Table.

GPIO A Peripheral Group Mux (GPIO16 to 31)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-15 GPAGMUX2 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-24 GPAGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO31R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO30R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO29R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO28R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO27R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO26R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO25R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO24R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO23R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO22R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO21R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO20R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO19R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO18R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO17R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO16R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.12 GPACSEL1 Register (Offset = 28h) [Reset = 00000000h]

GPACSEL1 is shown in Figure 14-16 and described in Table 14-25.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-16 GPACSEL1 Register
31302928272625242322212019181716
GPIO7GPIO6GPIO5GPIO4
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-25 GPACSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO7R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO6R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO5R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO4R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO3R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO2R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO1R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO0R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.13 GPACSEL2 Register (Offset = 2Ah) [Reset = 00000000h]

GPACSEL2 is shown in Figure 14-17 and described in Table 14-26.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-17 GPACSEL2 Register
31302928272625242322212019181716
GPIO15GPIO14GPIO13GPIO12
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-26 GPACSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO15R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO14R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO13R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO12R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO11R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO10R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO9R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO8R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.14 GPACSEL3 Register (Offset = 2Ch) [Reset = 00000000h]

GPACSEL3 is shown in Figure 14-18 and described in Table 14-27.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-18 GPACSEL3 Register
31302928272625242322212019181716
GPIO23GPIO22GPIO21GPIO20
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-27 GPACSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO23R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO22R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO21R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO20R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO19R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO18R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO17R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO16R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.15 GPACSEL4 Register (Offset = 2Eh) [Reset = 00000000h]

GPACSEL4 is shown in Figure 14-19 and described in Table 14-28.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-19 GPACSEL4 Register
31302928272625242322212019181716
GPIO31GPIO30GPIO29GPIO28
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-28 GPACSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO31R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO30R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO29R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO28R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO27R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO26R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO25R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO24R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.16 GPALOCK Register (Offset = 3Ch) [Reset = 00000000h]

GPALOCK is shown in Figure 14-20 and described in Table 14-29.

Return to the Summary Table.

GPIO A Lock Configuration Register (GPIO0 to 31)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-20 GPALOCK Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-29 GPALOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO30R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO29R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO28R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO27R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO26R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO25R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO24R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO23R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO22R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO21R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO20R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO19R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO18R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO17R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO16R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO15R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO14R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO13R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO12R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO11R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO10R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO9R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO8R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO7R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO6R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO5R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO4R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO3R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO2R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO1R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO0R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14.11.2.17 GPACR Register (Offset = 3Eh) [Reset = 00000000h]

GPACR is shown in Figure 14-21 and described in Table 14-30.

Return to the Summary Table.

GPIO A Lock Commit Register (GPIO0 to 31)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-21 GPACR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-30 GPACR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO30R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO29R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO28R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO27R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO26R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO25R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO24R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO23R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO22R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO21R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO20R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO19R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO18R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO17R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO16R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO15R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO14R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO13R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO12R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO11R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO10R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO9R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO8R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO7R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO6R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO5R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO4R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO3R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO2R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO1R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO0R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14.11.2.18 GPBCTRL Register (Offset = 40h) [Reset = 00000000h]

GPBCTRL is shown in Figure 14-22 and described in Table 14-31.

Return to the Summary Table.

GPIO B Qualification Sampling Period Control (GPIO32 to 63)

Figure 14-22 GPBCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-31 GPBCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO56 to GPIO63:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO48 to GPIO55:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO40 to GPIO47:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO32 to GPIO39:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.19 GPBQSEL1 Register (Offset = 42h) [Reset = 00000CC0h]

GPBQSEL1 is shown in Figure 14-23 and described in Table 14-32.

Return to the Summary Table.

GPIO B Qualifier Select 1 Register (GPIO32 to 47)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-23 GPBQSEL1 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-3hR/W-0hR/W-3hR/W-0hR/W-0hR/W-0h
Table 14-32 GPBQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO47R/W0hSelect input qualification type for GPIO47:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO46R/W0hSelect input qualification type for GPIO46:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO45R/W0hSelect input qualification type for GPIO45:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO44R/W0hSelect input qualification type for GPIO44:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO43R/W0hSelect input qualification type for GPIO43:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO42R/W0hSelect input qualification type for GPIO42:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO41R/W0hSelect input qualification type for GPIO41:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO40R/W0hSelect input qualification type for GPIO40:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO39R/W0hSelect input qualification type for GPIO39:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO38R/W0hSelect input qualification type for GPIO38:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO37R/W3hSelect input qualification type for GPIO37:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO36R/W0hSelect input qualification type for GPIO36:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO35R/W3hSelect input qualification type for GPIO35:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO34R/W0hSelect input qualification type for GPIO34:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO33R/W0hSelect input qualification type for GPIO33:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO32R/W0hSelect input qualification type for GPIO32:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.20 GPBQSEL2 Register (Offset = 44h) [Reset = 00000000h]

GPBQSEL2 is shown in Figure 14-24 and described in Table 14-33.

Return to the Summary Table.

GPIO B Qualifier Select 2 Register (GPIO48 to 63)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-24 GPBQSEL2 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-33 GPBQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO63R/W0hSelect input qualification type for GPIO63:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO62R/W0hSelect input qualification type for GPIO62:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO61R/W0hSelect input qualification type for GPIO61:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO60R/W0hSelect input qualification type for GPIO60:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO59R/W0hSelect input qualification type for GPIO59:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO58R/W0hSelect input qualification type for GPIO58:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO57R/W0hSelect input qualification type for GPIO57:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO56R/W0hSelect input qualification type for GPIO56:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO55R/W0hSelect input qualification type for GPIO55:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO54R/W0hSelect input qualification type for GPIO54:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO53R/W0hSelect input qualification type for GPIO53:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO52R/W0hSelect input qualification type for GPIO52:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO51R/W0hSelect input qualification type for GPIO51:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO50R/W0hSelect input qualification type for GPIO50:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO49R/W0hSelect input qualification type for GPIO49:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO48R/W0hSelect input qualification type for GPIO48:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.21 GPBMUX1 Register (Offset = 46h) [Reset = 00000CC0h]

GPBMUX1 is shown in Figure 14-25 and described in Table 14-34.

Return to the Summary Table.

GPIO B Mux 1 Register (GPIO32 to 47)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-25 GPBMUX1 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-3hR/W-0hR/W-3hR/W-0hR/W-0hR/W-0h
Table 14-34 GPBMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO47R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO46R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO45R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO44R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO43R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO42R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO41R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO40R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO39R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO38R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO37R/W3hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO36R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO35R/W3hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO34R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO33R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO32R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.22 GPBMUX2 Register (Offset = 48h) [Reset = 00000000h]

GPBMUX2 is shown in Figure 14-26 and described in Table 14-35.

Return to the Summary Table.

GPIO B Mux 2 Register (GPIO48 to 63)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-26 GPBMUX2 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-35 GPBMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO63R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO62R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO61R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO60R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO59R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO58R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO57R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO56R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO55R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO54R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO53R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO52R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO51R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO50R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO49R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO48R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.23 GPBDIR Register (Offset = 4Ah) [Reset = 00000000h]

GPBDIR is shown in Figure 14-27 and described in Table 14-36.

Return to the Summary Table.

GPIO B Direction Register (GPIO32 to 63)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-27 GPBDIR Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-36 GPBDIR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

30GPIO62R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

29GPIO61R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

28GPIO60R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

27GPIO59R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

26GPIO58R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

25GPIO57R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

24GPIO56R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

23GPIO55R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

22GPIO54R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

21GPIO53R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

20GPIO52R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

19GPIO51R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

18GPIO50R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO49R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16GPIO48R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

15GPIO47R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14GPIO46R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO45R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12GPIO44R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

11GPIO43R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

10GPIO42R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

9GPIO41R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

8GPIO40R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO39R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO38R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO37R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO36R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO35R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO34R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO33R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO32R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.24 GPBPUD Register (Offset = 4Ch) [Reset = FFFFFFFFh]

GPBPUD is shown in Figure 14-28 and described in Table 14-37.

Return to the Summary Table.

GPIO B Pull Up Disable Register (GPIO32 to 63)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-28 GPBPUD Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-37 GPBPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO62R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO61R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO60R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO59R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO58R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO57R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO56R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO55R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO54R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO53R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO52R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO51R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO50R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO49R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO48R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO47R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO46R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO45R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO44R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO43R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO42R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO41R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO40R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO39R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO38R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO37R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO36R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO35R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO34R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO33R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO32R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14.11.2.25 GPBINV Register (Offset = 50h) [Reset = 00000000h]

GPBINV is shown in Figure 14-29 and described in Table 14-38.

Return to the Summary Table.

GPIO B Input Polarity Invert Registers (GPIO32 to 63)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-29 GPBINV Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-38 GPBINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO62R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO61R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO60R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO59R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO58R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO57R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO56R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO55R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO54R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO53R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO52R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO51R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO50R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO49R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO48R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO47R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO46R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO45R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO44R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO43R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO42R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO41R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO40R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO39R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO38R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO37R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO36R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO35R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO34R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO33R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO32R/W0hInput inversion control for this pin

Reset type: SYSRSn

14.11.2.26 GPBODR Register (Offset = 52h) [Reset = 00000000h]

GPBODR is shown in Figure 14-30 and described in Table 14-39.

Return to the Summary Table.

GPIO B Open Drain Output Register (GPIO32 to GPIO63)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-30 GPBODR Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-39 GPBODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

30GPIO62R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

29GPIO61R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

28GPIO60R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

27GPIO59R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

26GPIO58R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

25GPIO57R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

24GPIO56R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

23GPIO55R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

22GPIO54R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

21GPIO53R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

20GPIO52R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

19GPIO51R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

18GPIO50R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO49R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16GPIO48R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

15GPIO47R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14GPIO46R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO45R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12GPIO44R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

11GPIO43R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

10GPIO42R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

9GPIO41R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

8GPIO40R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO39R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO38R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO37R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO36R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO35R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO34R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO33R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO32R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.27 GPBAMSEL Register (Offset = 54h) [Reset = 00000000h]

GPBAMSEL is shown in Figure 14-31 and described in Table 14-40.

Return to the Summary Table.

GPIO B Analog Mode Select register (GPIO32 to GPIO63)

Selects between digital and analog functionality for GPIO pins.

0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t

Figure 14-31 GPBAMSEL Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDGPIO43GPIO42RESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-40 GPBAMSEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11GPIO43R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

10GPIO42R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

14.11.2.28 GPBGMUX1 Register (Offset = 60h) [Reset = 00000CC0h]

GPBGMUX1 is shown in Figure 14-32 and described in Table 14-41.

Return to the Summary Table.

GPIO B Peripheral Group Mux (GPIO32 to 47)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-32 GPBGMUX1 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-3hR/W-0hR/W-3hR/W-0hR/W-0hR/W-0h
Table 14-41 GPBGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO47R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO46R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO45R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO44R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO43R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO42R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO41R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO40R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO39R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO38R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO37R/W3hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO36R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO35R/W3hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO34R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO33R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO32R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.29 GPBGMUX2 Register (Offset = 62h) [Reset = 00000000h]

GPBGMUX2 is shown in Figure 14-33 and described in Table 14-42.

Return to the Summary Table.

GPIO B Peripheral Group Mux (GPIO48 to 63)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-33 GPBGMUX2 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-42 GPBGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO63R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO62R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO61R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO60R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO59R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO58R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO57R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO56R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO55R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO54R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO53R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO52R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO51R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO50R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO49R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO48R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.30 GPBCSEL1 Register (Offset = 68h) [Reset = 00000000h]

GPBCSEL1 is shown in Figure 14-34 and described in Table 14-43.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-34 GPBCSEL1 Register
31302928272625242322212019181716
GPIO39GPIO38GPIO37GPIO36
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-43 GPBCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO39R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO38R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO37R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO36R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO35R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO34R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO33R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO32R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.31 GPBCSEL2 Register (Offset = 6Ah) [Reset = 00000000h]

GPBCSEL2 is shown in Figure 14-35 and described in Table 14-44.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-35 GPBCSEL2 Register
31302928272625242322212019181716
GPIO47GPIO46GPIO45GPIO44
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-44 GPBCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO47R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO46R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO45R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO44R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO43R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO42R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO41R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO40R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.32 GPBCSEL3 Register (Offset = 6Ch) [Reset = 00000000h]

GPBCSEL3 is shown in Figure 14-36 and described in Table 14-45.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-36 GPBCSEL3 Register
31302928272625242322212019181716
GPIO55GPIO54GPIO53GPIO52
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-45 GPBCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO55R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO54R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO53R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO52R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO51R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO50R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO49R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO48R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.33 GPBCSEL4 Register (Offset = 6Eh) [Reset = 00000000h]

GPBCSEL4 is shown in Figure 14-37 and described in Table 14-46.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-37 GPBCSEL4 Register
31302928272625242322212019181716
GPIO63GPIO62GPIO61GPIO60
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-46 GPBCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO63R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO62R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO61R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO60R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO59R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO58R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO57R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO56R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.34 GPBLOCK Register (Offset = 7Ch) [Reset = 00000000h]

GPBLOCK is shown in Figure 14-38 and described in Table 14-47.

Return to the Summary Table.

GPIO B Lock Configuration Register (GPIO32 to 63)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-38 GPBLOCK Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-47 GPBLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO62R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO61R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO60R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO59R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO58R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO57R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO56R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO55R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO54R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO53R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO52R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO51R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO50R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO49R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO48R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO47R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO46R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO45R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO44R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO43R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO42R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO41R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO40R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO39R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO38R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO37R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO36R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO35R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO34R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO33R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO32R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14.11.2.35 GPBCR Register (Offset = 7Eh) [Reset = 00000000h]

GPBCR is shown in Figure 14-39 and described in Table 14-48.

Return to the Summary Table.

GPIO B Lock Commit Register (GPIO32 to 63)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-39 GPBCR Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-48 GPBCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO62R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO61R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO60R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO59R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO58R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO57R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO56R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO55R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO54R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO53R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO52R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO51R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO50R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO49R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO48R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO47R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO46R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO45R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO44R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO43R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO42R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO41R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO40R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO39R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO38R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO37R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO36R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO35R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO34R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO33R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO32R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14.11.2.36 GPCCTRL Register (Offset = 80h) [Reset = 00000000h]

GPCCTRL is shown in Figure 14-40 and described in Table 14-49.

Return to the Summary Table.

GPIO C Qualification Sampling Period Control (GPIO64 to 95)

Figure 14-40 GPCCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-49 GPCCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO88 to GPIO95:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO80 to GPIO87:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO72 to GPIO79:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO64 to GPIO71:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.37 GPCQSEL1 Register (Offset = 82h) [Reset = 00000000h]

GPCQSEL1 is shown in Figure 14-41 and described in Table 14-50.

Return to the Summary Table.

GPIO C Qualifier Select 1 Register (GPIO64 to 79)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-41 GPCQSEL1 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-50 GPCQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO79R/W0hSelect input qualification type for GPIO79:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO78R/W0hSelect input qualification type for GPIO78:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO77R/W0hSelect input qualification type for GPIO77:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO76R/W0hSelect input qualification type for GPIO76:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO75R/W0hSelect input qualification type for GPIO75:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO74R/W0hSelect input qualification type for GPIO74:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO73R/W0hSelect input qualification type for GPIO73:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO72R/W0hSelect input qualification type for GPIO72:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO71R/W0hSelect input qualification type for GPIO71:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO70R/W0hSelect input qualification type for GPIO70:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO69R/W0hSelect input qualification type for GPIO69:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO68R/W0hSelect input qualification type for GPIO68:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO67R/W0hSelect input qualification type for GPIO67:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO66R/W0hSelect input qualification type for GPIO66:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO65R/W0hSelect input qualification type for GPIO65:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO64R/W0hSelect input qualification type for GPIO64:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.38 GPCQSEL2 Register (Offset = 84h) [Reset = 00000000h]

GPCQSEL2 is shown in Figure 14-42 and described in Table 14-51.

Return to the Summary Table.

GPIO C Qualifier Select 2 Register (GPIO80 to 95)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-42 GPCQSEL2 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-51 GPCQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO95R/W0hSelect input qualification type for GPIO95:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO94R/W0hSelect input qualification type for GPIO94:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO93R/W0hSelect input qualification type for GPIO93:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO92R/W0hSelect input qualification type for GPIO92:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO91R/W0hSelect input qualification type for GPIO91:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO90R/W0hSelect input qualification type for GPIO90:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO89R/W0hSelect input qualification type for GPIO89:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO88R/W0hSelect input qualification type for GPIO88:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO87R/W0hSelect input qualification type for GPIO87:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO86R/W0hSelect input qualification type for GPIO86:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO85R/W0hSelect input qualification type for GPIO85:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO84R/W0hSelect input qualification type for GPIO84:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO83R/W0hSelect input qualification type for GPIO83:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO82R/W0hSelect input qualification type for GPIO82:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO81R/W0hSelect input qualification type for GPIO81:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO80R/W0hSelect input qualification type for GPIO80:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.39 GPCMUX1 Register (Offset = 86h) [Reset = 00000000h]

GPCMUX1 is shown in Figure 14-43 and described in Table 14-52.

Return to the Summary Table.

GPIO C Mux 1 Register (GPIO64 to 79)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-43 GPCMUX1 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-52 GPCMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO79R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO78R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO77R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO76R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO75R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO74R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO73R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO72R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO71R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO70R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO69R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO68R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO67R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO66R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO65R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO64R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.40 GPCMUX2 Register (Offset = 88h) [Reset = 00000000h]

GPCMUX2 is shown in Figure 14-44 and described in Table 14-53.

Return to the Summary Table.

GPIO C Mux 2 Register (GPIO80 to 95)
Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-44 GPCMUX2 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-53 GPCMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO95R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO94R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO93R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO92R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO91R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO90R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO89R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO88R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO87R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO86R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO85R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO84R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO83R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO82R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO81R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO80R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.41 GPCDIR Register (Offset = 8Ah) [Reset = 00000000h]

GPCDIR is shown in Figure 14-45 and described in Table 14-54.

Return to the Summary Table.

GPIO C Direction Register (GPIO64 to 95)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-45 GPCDIR Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-54 GPCDIR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

30GPIO94R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

29GPIO93R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

28GPIO92R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

27GPIO91R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

26GPIO90R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

25GPIO89R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

24GPIO88R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

23GPIO87R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

22GPIO86R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

21GPIO85R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

20GPIO84R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

19GPIO83R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

18GPIO82R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO81R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16GPIO80R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

15GPIO79R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14GPIO78R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO77R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12GPIO76R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

11GPIO75R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

10GPIO74R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

9GPIO73R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

8GPIO72R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO71R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO70R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO69R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO68R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO67R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO66R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO65R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO64R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.42 GPCPUD Register (Offset = 8Ch) [Reset = FFFFFFFFh]

GPCPUD is shown in Figure 14-46 and described in Table 14-55.

Return to the Summary Table.

GPIO C Pull Up Disable Register (GPIO64 to 95)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-46 GPCPUD Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-55 GPCPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO94R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO93R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO92R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO91R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO90R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO89R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO88R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO87R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO86R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO85R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO84R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO83R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO82R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO81R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO80R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO79R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO78R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO77R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO76R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO75R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO74R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO73R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO72R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO71R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO70R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO69R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO68R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO67R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO66R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO65R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO64R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14.11.2.43 GPCINV Register (Offset = 90h) [Reset = 00000000h]

GPCINV is shown in Figure 14-47 and described in Table 14-56.

Return to the Summary Table.

GPIO C Input Polarity Invert Registers (GPIO64 to 95)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-47 GPCINV Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-56 GPCINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO94R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO93R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO92R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO91R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO90R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO89R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO88R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO87R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO86R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO85R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO84R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO83R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO82R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO81R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO80R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO79R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO78R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO77R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO76R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO75R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO74R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO73R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO72R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO71R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO70R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO69R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO68R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO67R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO66R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO65R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO64R/W0hInput inversion control for this pin

Reset type: SYSRSn

14.11.2.44 GPCODR Register (Offset = 92h) [Reset = 00000000h]

GPCODR is shown in Figure 14-48 and described in Table 14-57.

Return to the Summary Table.

GPIO C Open Drain Output Register (GPIO64 to GPIO95)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-48 GPCODR Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-57 GPCODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

30GPIO94R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

29GPIO93R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

28GPIO92R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

27GPIO91R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

26GPIO90R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

25GPIO89R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

24GPIO88R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

23GPIO87R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

22GPIO86R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

21GPIO85R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

20GPIO84R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

19GPIO83R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

18GPIO82R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO81R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16GPIO80R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

15GPIO79R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14GPIO78R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO77R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12GPIO76R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

11GPIO75R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

10GPIO74R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

9GPIO73R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

8GPIO72R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO71R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO70R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO69R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO68R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO67R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO66R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO65R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO64R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.45 GPCGMUX1 Register (Offset = A0h) [Reset = 00000000h]

GPCGMUX1 is shown in Figure 14-49 and described in Table 14-58.

Return to the Summary Table.

GPIO C Peripheral Group Mux (GPIO64 to 79)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-49 GPCGMUX1 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-58 GPCGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO79R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO78R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO77R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO76R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO75R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO74R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO73R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO72R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO71R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO70R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO69R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO68R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO67R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO66R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO65R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO64R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.46 GPCGMUX2 Register (Offset = A2h) [Reset = 00000000h]

GPCGMUX2 is shown in Figure 14-50 and described in Table 14-59.

Return to the Summary Table.

GPIO C Peripheral Group Mux (GPIO80 to 95)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-50 GPCGMUX2 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-59 GPCGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO95R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO94R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO93R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO92R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO91R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO90R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO89R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO88R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO87R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO86R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO85R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO84R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO83R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO82R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO81R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO80R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.47 GPCCSEL1 Register (Offset = A8h) [Reset = 00000000h]

GPCCSEL1 is shown in Figure 14-51 and described in Table 14-60.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-51 GPCCSEL1 Register
31302928272625242322212019181716
GPIO71GPIO70GPIO69GPIO68
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-60 GPCCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO71R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO70R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO69R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO68R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO67R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO66R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO65R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO64R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.48 GPCCSEL2 Register (Offset = AAh) [Reset = 00000000h]

GPCCSEL2 is shown in Figure 14-52 and described in Table 14-61.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-52 GPCCSEL2 Register
31302928272625242322212019181716
GPIO79GPIO78GPIO77GPIO76
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-61 GPCCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO79R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO78R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO77R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO76R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO75R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO74R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO73R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO72R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.49 GPCCSEL3 Register (Offset = ACh) [Reset = 00000000h]

GPCCSEL3 is shown in Figure 14-53 and described in Table 14-62.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-53 GPCCSEL3 Register
31302928272625242322212019181716
GPIO87GPIO86GPIO85GPIO84
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-62 GPCCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO87R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO86R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO85R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO84R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO83R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO82R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO81R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO80R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.50 GPCCSEL4 Register (Offset = AEh) [Reset = 00000000h]

GPCCSEL4 is shown in Figure 14-54 and described in Table 14-63.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-54 GPCCSEL4 Register
31302928272625242322212019181716
GPIO95GPIO94GPIO93GPIO92
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-63 GPCCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO95R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO94R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO93R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO92R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO91R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO90R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO89R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO88R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.51 GPCLOCK Register (Offset = BCh) [Reset = 00000000h]

GPCLOCK is shown in Figure 14-55 and described in Table 14-64.

Return to the Summary Table.

GPIO C Lock Configuration Register (GPIO64 to 95)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-55 GPCLOCK Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-64 GPCLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO94R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO93R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO92R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO91R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO90R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO89R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO88R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO87R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO86R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO85R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO84R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO83R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO82R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO81R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO80R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO79R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO78R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO77R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO76R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO75R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO74R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO73R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO72R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO71R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO70R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO69R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO68R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO67R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO66R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO65R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO64R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14.11.2.52 GPCCR Register (Offset = BEh) [Reset = 00000000h]

GPCCR is shown in Figure 14-56 and described in Table 14-65.

Return to the Summary Table.

GPIO C Lock Commit Register (GPIO64 to 95)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-56 GPCCR Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-65 GPCCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO94R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO93R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO92R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO91R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO90R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO89R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO88R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO87R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO86R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO85R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO84R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO83R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO82R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO81R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO80R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO79R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO78R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO77R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO76R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO75R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO74R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO73R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO72R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO71R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO70R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO69R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO68R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO67R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO66R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO65R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO64R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14.11.2.53 GPDCTRL Register (Offset = C0h) [Reset = 00000000h]

GPDCTRL is shown in Figure 14-57 and described in Table 14-66.

Return to the Summary Table.

GPIO D Qualification Sampling Period Control (GPIO96 to 127)

Figure 14-57 GPDCTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-66 GPDCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO120 to GPIO127:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO112 to GPIO119:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO104 to GPIO111:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO96 to GPIO103:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.54 GPDQSEL1 Register (Offset = C2h) [Reset = 00000000h]

GPDQSEL1 is shown in Figure 14-58 and described in Table 14-67.

Return to the Summary Table.

GPIO D Qualifier Select 1 Register (GPIO96 to 111)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-58 GPDQSEL1 Register
3130292827262524
GPIO111GPIO110GPIO109GPIO108
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO103GPIO102GPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-67 GPDQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO111R/W0hSelect input qualification type for GPIO111:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO110R/W0hSelect input qualification type for GPIO110:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO109R/W0hSelect input qualification type for GPIO109:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO108R/W0hSelect input qualification type for GPIO108:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO107R/W0hSelect input qualification type for GPIO107:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO106R/W0hSelect input qualification type for GPIO106:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO105R/W0hSelect input qualification type for GPIO105:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO104R/W0hSelect input qualification type for GPIO104:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO103R/W0hSelect input qualification type for GPIO103:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO102R/W0hSelect input qualification type for GPIO102:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO101R/W0hSelect input qualification type for GPIO101:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO100R/W0hSelect input qualification type for GPIO100:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO99R/W0hSelect input qualification type for GPIO99:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO98R/W0hSelect input qualification type for GPIO98:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO97R/W0hSelect input qualification type for GPIO97:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO96R/W0hSelect input qualification type for GPIO96:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.55 GPDQSEL2 Register (Offset = C4h) [Reset = 00000000h]

GPDQSEL2 is shown in Figure 14-59 and described in Table 14-68.

Return to the Summary Table.

GPIO D Qualifier Select 2 Register (GPIO112 to 127)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-59 GPDQSEL2 Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO119RESERVEDRESERVEDGPIO116
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-68 GPDQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO127R/W0hSelect input qualification type for GPIO127:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO126R/W0hSelect input qualification type for GPIO126:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO125R/W0hSelect input qualification type for GPIO125:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO124R/W0hSelect input qualification type for GPIO124:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO123R/W0hSelect input qualification type for GPIO123:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO122R/W0hSelect input qualification type for GPIO122:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18RESERVEDR/W0hReserved
17-16GPIO120R/W0hSelect input qualification type for GPIO120:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO119R/W0hSelect input qualification type for GPIO119:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8GPIO116R/W0hSelect input qualification type for GPIO116:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO115R/W0hSelect input qualification type for GPIO115:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO114R/W0hSelect input qualification type for GPIO114:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO113R/W0hSelect input qualification type for GPIO113:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO112R/W0hSelect input qualification type for GPIO112:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.56 GPDMUX1 Register (Offset = C6h) [Reset = 00000000h]

GPDMUX1 is shown in Figure 14-60 and described in Table 14-69.

Return to the Summary Table.

GPIO D Mux 1 Register (GPIO96 to 111)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-60 GPDMUX1 Register
3130292827262524
GPIO111GPIO110GPIO109GPIO108
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO103GPIO102GPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-69 GPDMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO111R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO110R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO109R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO108R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO107R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO106R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO105R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO104R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO103R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO102R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO101R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO100R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO99R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO98R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO97R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO96R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.57 GPDMUX2 Register (Offset = C8h) [Reset = 00000000h]

GPDMUX2 is shown in Figure 14-61 and described in Table 14-70.

Return to the Summary Table.

GPIO D Mux 2 Register (GPIO112 to 127)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-61 GPDMUX2 Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO119RESERVEDRESERVEDGPIO116
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-70 GPDMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO127R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO126R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO125R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO124R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO123R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO122R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18RESERVEDR/W0hReserved
17-16GPIO120R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO119R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8GPIO116R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO115R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO114R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO113R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO112R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.58 GPDDIR Register (Offset = CAh) [Reset = 00000000h]

GPDDIR is shown in Figure 14-62 and described in Table 14-71.

Return to the Summary Table.

GPIO D Direction Register (GPIO96 to 127)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-62 GPDDIR Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119RESERVEDRESERVEDGPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-71 GPDDIR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

30GPIO126R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

29GPIO125R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

28GPIO124R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

27GPIO123R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

26GPIO122R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

25RESERVEDR/W0hReserved
24GPIO120R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

23GPIO119R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20GPIO116R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

19GPIO115R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

18GPIO114R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO113R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16GPIO112R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

15GPIO111R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14GPIO110R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO109R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12GPIO108R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

11GPIO107R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

10GPIO106R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

9GPIO105R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

8GPIO104R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO103R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO102R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO101R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO100R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO99R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO98R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO97R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO96R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.59 GPDPUD Register (Offset = CCh) [Reset = FFFFFFFFh]

GPDPUD is shown in Figure 14-63 and described in Table 14-72.

Return to the Summary Table.

GPIO D Pull Up Disable Register (GPIO96 to 127)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-63 GPDPUD Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122RESERVEDGPIO120
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO119RESERVEDRESERVEDGPIO116GPIO115GPIO114GPIO113GPIO112
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-72 GPDPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO126R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO125R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO124R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO123R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO122R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25RESERVEDR/W1hReserved
24GPIO120R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO119R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22RESERVEDR/W1hReserved
21RESERVEDR/W1hReserved
20GPIO116R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO115R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO114R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO113R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO112R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO111R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO110R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO109R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO108R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO107R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO106R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO105R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO104R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO103R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO102R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO101R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO100R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO99R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO98R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO97R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO96R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14.11.2.60 GPDINV Register (Offset = D0h) [Reset = 00000000h]

GPDINV is shown in Figure 14-64 and described in Table 14-73.

Return to the Summary Table.

GPIO D Input Polarity Invert Registers (GPIO96 to 127)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-64 GPDINV Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119RESERVEDRESERVEDGPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-73 GPDINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO126R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO125R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO124R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO123R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO122R/W0hInput inversion control for this pin

Reset type: SYSRSn

25RESERVEDR/W0hReserved
24GPIO120R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO119R/W0hInput inversion control for this pin

Reset type: SYSRSn

22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20GPIO116R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO115R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO114R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO113R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO112R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO111R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO110R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO109R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO108R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO107R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO106R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO105R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO104R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO103R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO102R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO101R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO100R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO99R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO98R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO97R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO96R/W0hInput inversion control for this pin

Reset type: SYSRSn

14.11.2.61 GPDODR Register (Offset = D2h) [Reset = 00000000h]

GPDODR is shown in Figure 14-65 and described in Table 14-74.

Return to the Summary Table.

GPIO D Open Drain Output Register (GPIO96 to GPIO127)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-65 GPDODR Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119RESERVEDRESERVEDGPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-74 GPDODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

30GPIO126R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

29GPIO125R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

28GPIO124R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

27GPIO123R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

26GPIO122R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

25RESERVEDR/W0hReserved
24GPIO120R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

23GPIO119R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20GPIO116R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

19GPIO115R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

18GPIO114R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO113R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16GPIO112R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

15GPIO111R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14GPIO110R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO109R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12GPIO108R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

11GPIO107R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

10GPIO106R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

9GPIO105R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

8GPIO104R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO103R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO102R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO101R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO100R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO99R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO98R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO97R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO96R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.62 GPDGMUX1 Register (Offset = E0h) [Reset = 00000000h]

GPDGMUX1 is shown in Figure 14-66 and described in Table 14-75.

Return to the Summary Table.

GPIO D Peripheral Group Mux (GPIO96 to 111)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-66 GPDGMUX1 Register
3130292827262524
GPIO111GPIO110GPIO109GPIO108
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO103GPIO102GPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-75 GPDGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO111R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO110R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO109R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO108R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO107R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO106R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO105R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO104R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO103R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO102R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO101R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO100R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO99R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO98R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO97R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO96R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.63 GPDGMUX2 Register (Offset = E2h) [Reset = 00000000h]

GPDGMUX2 is shown in Figure 14-67 and described in Table 14-76.

Return to the Summary Table.

GPIO D Peripheral Group Mux (GPIO112 to 127)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-67 GPDGMUX2 Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO119RESERVEDRESERVEDGPIO116
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-76 GPDGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO127R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO126R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO125R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO124R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO123R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO122R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18RESERVEDR/W0hReserved
17-16GPIO120R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO119R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8GPIO116R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO115R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO114R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO113R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO112R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.64 GPDCSEL1 Register (Offset = E8h) [Reset = 00000000h]

GPDCSEL1 is shown in Figure 14-68 and described in Table 14-77.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-68 GPDCSEL1 Register
31302928272625242322212019181716
GPIO103GPIO102GPIO101GPIO100
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-77 GPDCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO103R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO102R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO101R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO100R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO99R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO98R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO97R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO96R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.65 GPDCSEL2 Register (Offset = EAh) [Reset = 00000000h]

GPDCSEL2 is shown in Figure 14-69 and described in Table 14-78.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-69 GPDCSEL2 Register
31302928272625242322212019181716
GPIO111GPIO110GPIO109GPIO108
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-78 GPDCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO111R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO110R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO109R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO108R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO107R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO106R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO105R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO104R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.66 GPDCSEL3 Register (Offset = ECh) [Reset = 00000000h]

GPDCSEL3 is shown in Figure 14-70 and described in Table 14-79.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-70 GPDCSEL3 Register
31302928272625242322212019181716
GPIO119RESERVEDRESERVEDGPIO116
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-79 GPDCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO119R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16GPIO116R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO115R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO114R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO113R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO112R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.67 GPDCSEL4 Register (Offset = EEh) [Reset = 00000000h]

GPDCSEL4 is shown in Figure 14-71 and described in Table 14-80.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-71 GPDCSEL4 Register
31302928272625242322212019181716
GPIO127GPIO126GPIO125GPIO124
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-80 GPDCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO127R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO126R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO125R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO124R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO123R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO122R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4RESERVEDR/W0hReserved
3-0GPIO120R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.68 GPDLOCK Register (Offset = FCh) [Reset = 00000000h]

GPDLOCK is shown in Figure 14-72 and described in Table 14-81.

Return to the Summary Table.

GPIO D Lock Configuration Register (GPIO96 to 127)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-72 GPDLOCK Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122RESERVEDGPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119RESERVEDRESERVEDGPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-81 GPDLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO126R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO125R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO124R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO123R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO122R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25RESERVEDR/W0hReserved
24GPIO120R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO119R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20GPIO116R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO115R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO114R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO113R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO112R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO111R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO110R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO109R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO108R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO107R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO106R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO105R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO104R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO103R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO102R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO101R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO100R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO99R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO98R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO97R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO96R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14.11.2.69 GPDCR Register (Offset = FEh) [Reset = 00000000h]

GPDCR is shown in Figure 14-73 and described in Table 14-82.

Return to the Summary Table.

GPIO D Lock Commit Register (GPIO96 to 127)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-73 GPDCR Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122RESERVEDGPIO120
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO119RESERVEDRESERVEDGPIO116GPIO115GPIO114GPIO113GPIO112
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-82 GPDCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO126R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO125R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO124R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO123R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO122R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25RESERVEDR/WSonce0hReserved
24GPIO120R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO119R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22RESERVEDR/WSonce0hReserved
21RESERVEDR/WSonce0hReserved
20GPIO116R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO115R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO114R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO113R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO112R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO111R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO110R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO109R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO108R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO107R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO106R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO105R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO104R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO103R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO102R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO101R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO100R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO99R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO98R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO97R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO96R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14.11.2.70 GPECTRL Register (Offset = 100h) [Reset = 00000000h]

GPECTRL is shown in Figure 14-74 and described in Table 14-83.

Return to the Summary Table.

GPIO E Qualification Sampling Period Control (GPIO128 to 159)

Figure 14-74 GPECTRL Register
313029282726252423222120191817161514131211109876543210
QUALPRD3QUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-83 GPECTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24QUALPRD3R/W0hQualification sampling period for GPIO152 to GPIO159:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

23-16QUALPRD2R/W0hQualification sampling period for GPIO144 to GPIO151:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

15-8QUALPRD1R/W0hQualification sampling period for GPIO136 to GPIO143:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO128 to GPIO135:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.71 GPEQSEL1 Register (Offset = 102h) [Reset = 00000000h]

GPEQSEL1 is shown in Figure 14-75 and described in Table 14-84.

Return to the Summary Table.

GPIO E Qualifier Select 1 Register (GPIO128 to 143)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-75 GPEQSEL1 Register
3130292827262524
RESERVEDGPIO142GPIO141RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO134GPIO133GPIO132
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-84 GPEQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28GPIO142R/W0hSelect input qualification type for GPIO142:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO141R/W0hSelect input qualification type for GPIO141:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12GPIO134R/W0hSelect input qualification type for GPIO134:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO133R/W0hSelect input qualification type for GPIO133:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO132R/W0hSelect input qualification type for GPIO132:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO131R/W0hSelect input qualification type for GPIO131:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO130R/W0hSelect input qualification type for GPIO130:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO129R/W0hSelect input qualification type for GPIO129:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO128R/W0hSelect input qualification type for GPIO128:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.72 GPEQSEL2 Register (Offset = 104h) [Reset = 00000000h]

GPEQSEL2 is shown in Figure 14-76 and described in Table 14-85.

Return to the Summary Table.

GPIO E Qualifier Select 2 Register (GPIO144 to 159)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-76 GPEQSEL2 Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO151GPIO150GPIO149GPIO148
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-85 GPEQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO159R/W0hSelect input qualification type for GPIO159:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO158R/W0hSelect input qualification type for GPIO158:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO157R/W0hSelect input qualification type for GPIO157:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO156R/W0hSelect input qualification type for GPIO156:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO155R/W0hSelect input qualification type for GPIO155:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO154R/W0hSelect input qualification type for GPIO154:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO153R/W0hSelect input qualification type for GPIO153:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO152R/W0hSelect input qualification type for GPIO152:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO151R/W0hSelect input qualification type for GPIO151:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO150R/W0hSelect input qualification type for GPIO150:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO149R/W0hSelect input qualification type for GPIO149:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO148R/W0hSelect input qualification type for GPIO148:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO147R/W0hSelect input qualification type for GPIO147:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO146R/W0hSelect input qualification type for GPIO146:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO145R/W0hSelect input qualification type for GPIO145:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0RESERVEDR/W0hReserved

14.11.2.73 GPEMUX1 Register (Offset = 106h) [Reset = 00000000h]

GPEMUX1 is shown in Figure 14-77 and described in Table 14-86.

Return to the Summary Table.

GPIO E Mux 1 Register (GPIO128 to 143)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-77 GPEMUX1 Register
3130292827262524
RESERVEDGPIO142GPIO141RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO134GPIO133GPIO132
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-86 GPEMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28GPIO142R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO141R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12GPIO134R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO133R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO132R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO131R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO130R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO129R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO128R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.74 GPEMUX2 Register (Offset = 108h) [Reset = 00000000h]

GPEMUX2 is shown in Figure 14-78 and described in Table 14-87.

Return to the Summary Table.

GPIO E Mux 2 Register (GPIO144 to 159)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-78 GPEMUX2 Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO151GPIO150GPIO149GPIO148
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-87 GPEMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO159R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO158R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO157R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO156R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO155R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO154R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO153R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO152R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO151R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO150R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO149R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO148R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO147R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO146R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO145R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0RESERVEDR/W0hReserved

14.11.2.75 GPEDIR Register (Offset = 10Ah) [Reset = 00000000h]

GPEDIR is shown in Figure 14-79 and described in Table 14-88.

Return to the Summary Table.

GPIO E Direction Register (GPIO128 to 159)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-79 GPEDIR Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO142GPIO141RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-88 GPEDIR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

30GPIO158R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

29GPIO157R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

28GPIO156R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

27GPIO155R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

26GPIO154R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

25GPIO153R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

24GPIO152R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

23GPIO151R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

22GPIO150R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

21GPIO149R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

20GPIO148R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

19GPIO147R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

18GPIO146R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO145R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14GPIO142R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO141R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6GPIO134R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO133R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO132R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO131R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO130R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO129R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO128R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.76 GPEPUD Register (Offset = 10Ch) [Reset = FFFFFFFFh]

GPEPUD is shown in Figure 14-80 and described in Table 14-89.

Return to the Summary Table.

GPIO E Pull Up Disable Register (GPIO128 to 159)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-80 GPEPUD Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145RESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
RESERVEDGPIO142GPIO141RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
RESERVEDGPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-89 GPEPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO158R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO157R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO156R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO155R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO154R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO153R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO152R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO151R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO150R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO149R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO148R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO147R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO146R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO145R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16RESERVEDR/W1hReserved
15RESERVEDR/W1hReserved
14GPIO142R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO141R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12RESERVEDR/W1hReserved
11RESERVEDR/W1hReserved
10RESERVEDR/W1hReserved
9RESERVEDR/W1hReserved
8RESERVEDR/W1hReserved
7RESERVEDR/W1hReserved
6GPIO134R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO133R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO132R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO131R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO130R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO129R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO128R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14.11.2.77 GPEINV Register (Offset = 110h) [Reset = 00000000h]

GPEINV is shown in Figure 14-81 and described in Table 14-90.

Return to the Summary Table.

GPIO E Input Polarity Invert Registers (GPIO128 to 159)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-81 GPEINV Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO142GPIO141RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-90 GPEINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO158R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO157R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO156R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO155R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO154R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO153R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO152R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO151R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO150R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO149R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO148R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO147R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO146R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO145R/W0hInput inversion control for this pin

Reset type: SYSRSn

16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14GPIO142R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO141R/W0hInput inversion control for this pin

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6GPIO134R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO133R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO132R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO131R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO130R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO129R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO128R/W0hInput inversion control for this pin

Reset type: SYSRSn

14.11.2.78 GPEODR Register (Offset = 112h) [Reset = 00000000h]

GPEODR is shown in Figure 14-82 and described in Table 14-91.

Return to the Summary Table.

GPIO E Open Drain Output Register (GPIO128 to GPIO159)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-82 GPEODR Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO142GPIO141RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-91 GPEODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

30GPIO158R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

29GPIO157R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

28GPIO156R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

27GPIO155R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

26GPIO154R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

25GPIO153R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

24GPIO152R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

23GPIO151R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

22GPIO150R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

21GPIO149R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

20GPIO148R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

19GPIO147R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

18GPIO146R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO145R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14GPIO142R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO141R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6GPIO134R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO133R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO132R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO131R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO130R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO129R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO128R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.79 GPEGMUX1 Register (Offset = 120h) [Reset = 00000000h]

GPEGMUX1 is shown in Figure 14-83 and described in Table 14-92.

Return to the Summary Table.

GPIO E Peripheral Group Mux (GPIO128 to 143)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-83 GPEGMUX1 Register
3130292827262524
RESERVEDGPIO142GPIO141RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO134GPIO133GPIO132
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-92 GPEGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28GPIO142R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO141R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12GPIO134R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO133R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO132R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO131R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO130R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO129R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO128R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.80 GPEGMUX2 Register (Offset = 122h) [Reset = 00000000h]

GPEGMUX2 is shown in Figure 14-84 and described in Table 14-93.

Return to the Summary Table.

GPIO E Peripheral Group Mux (GPIO144 to 159)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-84 GPEGMUX2 Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO151GPIO150GPIO149GPIO148
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-93 GPEGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO159R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO158R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO157R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO156R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO155R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO154R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO153R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO152R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO151R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO150R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO149R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO148R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO147R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO146R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO145R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0RESERVEDR/W0hReserved

14.11.2.81 GPECSEL1 Register (Offset = 128h) [Reset = 00000000h]

GPECSEL1 is shown in Figure 14-85 and described in Table 14-94.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-85 GPECSEL1 Register
31302928272625242322212019181716
RESERVEDGPIO134GPIO133GPIO132
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-94 GPECSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24GPIO134R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO133R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO132R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO131R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO130R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO129R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO128R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.82 GPECSEL2 Register (Offset = 12Ah) [Reset = 00000000h]

GPECSEL2 is shown in Figure 14-86 and described in Table 14-95.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-86 GPECSEL2 Register
31302928272625242322212019181716
RESERVEDGPIO142GPIO141RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-95 GPECSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24GPIO142R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO141R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

14.11.2.83 GPECSEL3 Register (Offset = 12Ch) [Reset = 00000000h]

GPECSEL3 is shown in Figure 14-87 and described in Table 14-96.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-87 GPECSEL3 Register
31302928272625242322212019181716
GPIO151GPIO150GPIO149GPIO148
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-96 GPECSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO151R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO150R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO149R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO148R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO147R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO146R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO145R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0RESERVEDR/W0hReserved

14.11.2.84 GPECSEL4 Register (Offset = 12Eh) [Reset = 00000000h]

GPECSEL4 is shown in Figure 14-88 and described in Table 14-97.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-88 GPECSEL4 Register
31302928272625242322212019181716
GPIO159GPIO158GPIO157GPIO156
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-97 GPECSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO159R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO158R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO157R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO156R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO155R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO154R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO153R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO152R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.85 GPELOCK Register (Offset = 13Ch) [Reset = 00000000h]

GPELOCK is shown in Figure 14-89 and described in Table 14-98.

Return to the Summary Table.

GPIO E Lock Configuration Register (GPIO128 to 159)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-89 GPELOCK Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145RESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDGPIO142GPIO141RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-98 GPELOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO158R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO157R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO156R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO155R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO154R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO153R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO152R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO151R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO150R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO149R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO148R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO147R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO146R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO145R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14GPIO142R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO141R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6GPIO134R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO133R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO132R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO131R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO130R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO129R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO128R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14.11.2.86 GPECR Register (Offset = 13Eh) [Reset = 00000000h]

GPECR is shown in Figure 14-90 and described in Table 14-99.

Return to the Summary Table.

GPIO E Lock Commit Register (GPIO128 to 159)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-90 GPECR Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145RESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
RESERVEDGPIO142GPIO141RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
RESERVEDGPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-99 GPECR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO158R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO157R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO156R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO155R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO154R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO153R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO152R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO151R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO150R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO149R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO148R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO147R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO146R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO145R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16RESERVEDR/WSonce0hReserved
15RESERVEDR/WSonce0hReserved
14GPIO142R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO141R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12RESERVEDR/WSonce0hReserved
11RESERVEDR/WSonce0hReserved
10RESERVEDR/WSonce0hReserved
9RESERVEDR/WSonce0hReserved
8RESERVEDR/WSonce0hReserved
7RESERVEDR/WSonce0hReserved
6GPIO134R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO133R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO132R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO131R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO130R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO129R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO128R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14.11.2.87 GPFCTRL Register (Offset = 140h) [Reset = 00000000h]

GPFCTRL is shown in Figure 14-91 and described in Table 14-100.

Return to the Summary Table.

GPIO F Qualification Sampling Period Control (GPIO160 to 191)

Figure 14-91 GPFCTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDQUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-100 GPFCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0hReserved
23-16RESERVEDR/W0hReserved
15-8QUALPRD1R/W0hQualification sampling period for GPIO168:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO160 to GPIO167:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.88 GPFQSEL1 Register (Offset = 142h) [Reset = 00000000h]

GPFQSEL1 is shown in Figure 14-92 and described in Table 14-101.

Return to the Summary Table.

GPIO F Qualifier Select 1 Register (GPIO160 to 168)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-92 GPFQSEL1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-101 GPFQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16GPIO168R/W0hSelect input qualification type for GPIO168:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO167R/W0hSelect input qualification type for GPIO167:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO166R/W0hSelect input qualification type for GPIO166:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO165R/W0hSelect input qualification type for GPIO165:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO164R/W0hSelect input qualification type for GPIO164:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO163R/W0hSelect input qualification type for GPIO163:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO162R/W0hSelect input qualification type for GPIO162:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO161R/W0hSelect input qualification type for GPIO161:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO160R/W0hSelect input qualification type for GPIO160:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.89 GPFQSEL2 Register (Offset = 144h) [Reset = 00000000h]

GPFQSEL2 is shown in Figure 14-93 and described in Table 14-102.

Return to the Summary Table.

GPIO F Qualifier Select 2 Register (GPIO176 to 191)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-93 GPFQSEL2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-102 GPFQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

14.11.2.90 GPFMUX1 Register (Offset = 146h) [Reset = 00000000h]

GPFMUX1 is shown in Figure 14-94 and described in Table 14-103.

Return to the Summary Table.

GPIO F Mux 1 Register (GPIO160 to 175)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-94 GPFMUX1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-103 GPFMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16GPIO168R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO167R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO166R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO165R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO164R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO163R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO162R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO161R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO160R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.91 GPFMUX2 Register (Offset = 148h) [Reset = 00000000h]

GPFMUX2 is shown in Figure 14-95 and described in Table 14-104.

Return to the Summary Table.

GPIO F Mux 2 Register (GPIO176 to 191)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-95 GPFMUX2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-104 GPFMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

14.11.2.92 GPFDIR Register (Offset = 14Ah) [Reset = 00000000h]

GPFDIR is shown in Figure 14-96 and described in Table 14-105.

Return to the Summary Table.

GPIO F Direction Register (GPIO160 to 191)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-96 GPFDIR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-105 GPFDIR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO167R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO166R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO165R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO164R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO163R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO162R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO161R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO160R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.93 GPFPUD Register (Offset = 14Ch) [Reset = FFFFFFFFh]

GPFPUD is shown in Figure 14-97 and described in Table 14-106.

Return to the Summary Table.

GPIO F Pull Up Disable Register (GPIO160 to 191)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-97 GPFPUD Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-106 GPFPUD Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W1hReserved
30RESERVEDR/W1hReserved
29RESERVEDR/W1hReserved
28RESERVEDR/W1hReserved
27RESERVEDR/W1hReserved
26RESERVEDR/W1hReserved
25RESERVEDR/W1hReserved
24RESERVEDR/W1hReserved
23RESERVEDR/W1hReserved
22RESERVEDR/W1hReserved
21RESERVEDR/W1hReserved
20RESERVEDR/W1hReserved
19RESERVEDR/W1hReserved
18RESERVEDR/W1hReserved
17RESERVEDR/W1hReserved
16RESERVEDR/W1hReserved
15RESERVEDR/W1hReserved
14RESERVEDR/W1hReserved
13RESERVEDR/W1hReserved
12RESERVEDR/W1hReserved
11RESERVEDR/W1hReserved
10RESERVEDR/W1hReserved
9RESERVEDR/W1hReserved
8GPIO168R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO167R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO166R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5GPIO165R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

4GPIO164R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

3GPIO163R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

2GPIO162R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

1GPIO161R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

0GPIO160R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14.11.2.94 GPFINV Register (Offset = 150h) [Reset = 00000000h]

GPFINV is shown in Figure 14-98 and described in Table 14-107.

Return to the Summary Table.

GPIO F Input Polarity Invert Registers (GPIO160 to 191)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-98 GPFINV Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-107 GPFINV Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO167R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO166R/W0hInput inversion control for this pin

Reset type: SYSRSn

5GPIO165R/W0hInput inversion control for this pin

Reset type: SYSRSn

4GPIO164R/W0hInput inversion control for this pin

Reset type: SYSRSn

3GPIO163R/W0hInput inversion control for this pin

Reset type: SYSRSn

2GPIO162R/W0hInput inversion control for this pin

Reset type: SYSRSn

1GPIO161R/W0hInput inversion control for this pin

Reset type: SYSRSn

0GPIO160R/W0hInput inversion control for this pin

Reset type: SYSRSn

14.11.2.95 GPFODR Register (Offset = 152h) [Reset = 00000000h]

GPFODR is shown in Figure 14-99 and described in Table 14-108.

Return to the Summary Table.

GPIO F Open Drain Output Register (GPIO160 to GPIO191)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-99 GPFODR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-108 GPFODR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO167R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO166R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO165R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO164R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO163R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO162R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO161R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO160R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.96 GPFGMUX1 Register (Offset = 160h) [Reset = 00000000h]

GPFGMUX1 is shown in Figure 14-100 and described in Table 14-109.

Return to the Summary Table.

GPIO F Peripheral Group Mux (GPIO160 to 175)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-100 GPFGMUX1 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-109 GPFGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16GPIO168R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO167R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO166R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO165R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO164R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO163R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO162R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO161R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO160R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.97 GPFGMUX2 Register (Offset = 162h) [Reset = 00000000h]

GPFGMUX2 is shown in Figure 14-101 and described in Table 14-110.

Return to the Summary Table.

GPIO F Peripheral Group Mux (GPIO176 to 191)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-101 GPFGMUX2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-110 GPFGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

14.11.2.98 GPFCSEL1 Register (Offset = 168h) [Reset = 00000000h]

GPFCSEL1 is shown in Figure 14-102 and described in Table 14-111.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-102 GPFCSEL1 Register
31302928272625242322212019181716
GPIO167GPIO166GPIO165GPIO164
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-111 GPFCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO167R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO166R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO165R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO164R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO163R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO162R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO161R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO160R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.99 GPFCSEL2 Register (Offset = 16Ah) [Reset = 00000000h]

GPFCSEL2 is shown in Figure 14-103 and described in Table 14-112.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-103 GPFCSEL2 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-112 GPFCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0GPIO168R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.100 GPFCSEL3 Register (Offset = 16Ch) [Reset = 00000000h]

GPFCSEL3 is shown in Figure 14-104 and described in Table 14-113.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-104 GPFCSEL3 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-113 GPFCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

14.11.2.101 GPFCSEL4 Register (Offset = 16Eh) [Reset = 00000000h]

GPFCSEL4 is shown in Figure 14-105 and described in Table 14-114.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-105 GPFCSEL4 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-114 GPFCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

14.11.2.102 GPFLOCK Register (Offset = 17Ch) [Reset = 00000000h]

GPFLOCK is shown in Figure 14-106 and described in Table 14-115.

Return to the Summary Table.

GPIO F Lock Configuration Register (GPIO160 to 191)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-106 GPFLOCK Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-115 GPFLOCK Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO167R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO166R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5GPIO165R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

4GPIO164R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

3GPIO163R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

2GPIO162R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

1GPIO161R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

0GPIO160R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14.11.2.103 GPFCR Register (Offset = 17Eh) [Reset = 00000000h]

GPFCR is shown in Figure 14-107 and described in Table 14-116.

Return to the Summary Table.

GPIO F Lock Commit Register (GPIO160 to 191)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-107 GPFCR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-116 GPFCR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WSonce0hReserved
30RESERVEDR/WSonce0hReserved
29RESERVEDR/WSonce0hReserved
28RESERVEDR/WSonce0hReserved
27RESERVEDR/WSonce0hReserved
26RESERVEDR/WSonce0hReserved
25RESERVEDR/WSonce0hReserved
24RESERVEDR/WSonce0hReserved
23RESERVEDR/WSonce0hReserved
22RESERVEDR/WSonce0hReserved
21RESERVEDR/WSonce0hReserved
20RESERVEDR/WSonce0hReserved
19RESERVEDR/WSonce0hReserved
18RESERVEDR/WSonce0hReserved
17RESERVEDR/WSonce0hReserved
16RESERVEDR/WSonce0hReserved
15RESERVEDR/WSonce0hReserved
14RESERVEDR/WSonce0hReserved
13RESERVEDR/WSonce0hReserved
12RESERVEDR/WSonce0hReserved
11RESERVEDR/WSonce0hReserved
10RESERVEDR/WSonce0hReserved
9RESERVEDR/WSonce0hReserved
8GPIO168R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO167R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO166R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5GPIO165R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

4GPIO164R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

3GPIO163R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

2GPIO162R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

1GPIO161R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

0GPIO160R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14.11.2.104 GPGCTRL Register (Offset = 180h) [Reset = 00000000h]

GPGCTRL is shown in Figure 14-108 and described in Table 14-117.

Return to the Summary Table.

GPIO G Qualification Sampling Period Control (GPIO192 to 223)

Figure 14-108 GPGCTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDQUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-117 GPGCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0hReserved
23-16RESERVEDR/W0hReserved
15-8QUALPRD1R/W0hQualification sampling period for GPIO200 to GPIO207:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

7-0QUALPRD0R/W0hQualification sampling period for GPIO192 to GPIO199:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.105 GPGQSEL1 Register (Offset = 182h) [Reset = 00000000h]

GPGQSEL1 is shown in Figure 14-109 and described in Table 14-118.

Return to the Summary Table.

GPIO G Qualifier Select 1 Register (GPIO192 to 207)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-109 GPGQSEL1 Register
3130292827262524
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO199GPIO198RESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-118 GPGQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO207R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO206R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO205R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO204R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO203R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO202R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO201R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO200R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO199R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO198R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

14.11.2.106 GPGQSEL2 Register (Offset = 184h) [Reset = F0000000h]

GPGQSEL2 is shown in Figure 14-110 and described in Table 14-119.

Return to the Summary Table.

GPIO G Qualifier Select 2 Register (GPIO208 to 223)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-110 GPGQSEL2 Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220
R/W-3hR/W-3hR/W-0hR/W-0h
2322212019181716
GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO215GPIO214GPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-119 GPGQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO223R/W3hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO222R/W3hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO221R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO220R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO219R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO218R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO217R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO216R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO215R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO214R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO213R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO212R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO211R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO210R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO209R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO208R/W0hSelect input qualification type for this GPIO:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.107 GPGMUX1 Register (Offset = 186h) [Reset = 00000000h]

GPGMUX1 is shown in Figure 14-111 and described in Table 14-120.

Return to the Summary Table.

GPIO G Mux 1 Register (GPIO192 to 207)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-111 GPGMUX1 Register
3130292827262524
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO199GPIO198RESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-120 GPGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO207R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO206R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO205R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO204R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO203R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO202R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO201R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO200R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO199R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO198R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

14.11.2.108 GPGMUX2 Register (Offset = 188h) [Reset = 50000000h]

GPGMUX2 is shown in Figure 14-112 and described in Table 14-121.

Return to the Summary Table.

GPIO G Mux 2 Register (GPIO208 to 223)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-112 GPGMUX2 Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220
R/W-1hR/W-1hR/W-0hR/W-0h
2322212019181716
GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO215GPIO214GPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-121 GPGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO223R/W1hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO222R/W1hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO221R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO220R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO219R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO218R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO217R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO216R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO215R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO214R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO213R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO212R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO211R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO210R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO209R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO208R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.109 GPGDIR Register (Offset = 18Ah) [Reset = 00000000h]

GPGDIR is shown in Figure 14-113 and described in Table 14-122.

Return to the Summary Table.

GPIO G Direction Register (GPIO192 to 223)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-113 GPGDIR Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-122 GPGDIR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

30GPIO222R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

29GPIO221R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

28GPIO220R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

27GPIO219R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

26GPIO218R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

25GPIO217R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

24GPIO216R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

23GPIO215R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

22GPIO214R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

21GPIO213R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

20GPIO212R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

19GPIO211R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

18GPIO210R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO209R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16GPIO208R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

15GPIO207R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14GPIO206R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO205R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12GPIO204R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

11GPIO203R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

10GPIO202R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

9GPIO201R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

8GPIO200R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO199R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO198R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

14.11.2.110 GPGPUD Register (Offset = 18Ch) [Reset = FFFFFFFFh]

GPGPUD is shown in Figure 14-114 and described in Table 14-123.

Return to the Summary Table.

GPIO G Pull Up Disable Register (GPIO192 to 223)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-114 GPGPUD Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-123 GPGPUD Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

30GPIO222R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

29GPIO221R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

28GPIO220R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

27GPIO219R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

26GPIO218R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

25GPIO217R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

24GPIO216R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

23GPIO215R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

22GPIO214R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

21GPIO213R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

20GPIO212R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

19GPIO211R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

18GPIO210R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

17GPIO209R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

16GPIO208R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

15GPIO207R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

14GPIO206R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

13GPIO205R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

12GPIO204R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

11GPIO203R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

10GPIO202R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

9GPIO201R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

8GPIO200R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

7GPIO199R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

6GPIO198R/W1hPull-Up Disable control for this pin

Reset type: SYSRSn

5RESERVEDR/W1hReserved
4RESERVEDR/W1hReserved
3RESERVEDR/W1hReserved
2RESERVEDR/W1hReserved
1RESERVEDR/W1hReserved
0RESERVEDR/W1hReserved

14.11.2.111 GPGINV Register (Offset = 190h) [Reset = 00000000h]

GPGINV is shown in Figure 14-115 and described in Table 14-124.

Return to the Summary Table.

GPIO G Input Polarity Invert Registers (GPIO192 to 223)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-115 GPGINV Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-124 GPGINV Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hInput inversion control for this pin

Reset type: SYSRSn

30GPIO222R/W0hInput inversion control for this pin

Reset type: SYSRSn

29GPIO221R/W0hInput inversion control for this pin

Reset type: SYSRSn

28GPIO220R/W0hInput inversion control for this pin

Reset type: SYSRSn

27GPIO219R/W0hInput inversion control for this pin

Reset type: SYSRSn

26GPIO218R/W0hInput inversion control for this pin

Reset type: SYSRSn

25GPIO217R/W0hInput inversion control for this pin

Reset type: SYSRSn

24GPIO216R/W0hInput inversion control for this pin

Reset type: SYSRSn

23GPIO215R/W0hInput inversion control for this pin

Reset type: SYSRSn

22GPIO214R/W0hInput inversion control for this pin

Reset type: SYSRSn

21GPIO213R/W0hInput inversion control for this pin

Reset type: SYSRSn

20GPIO212R/W0hInput inversion control for this pin

Reset type: SYSRSn

19GPIO211R/W0hInput inversion control for this pin

Reset type: SYSRSn

18GPIO210R/W0hInput inversion control for this pin

Reset type: SYSRSn

17GPIO209R/W0hInput inversion control for this pin

Reset type: SYSRSn

16GPIO208R/W0hInput inversion control for this pin

Reset type: SYSRSn

15GPIO207R/W0hInput inversion control for this pin

Reset type: SYSRSn

14GPIO206R/W0hInput inversion control for this pin

Reset type: SYSRSn

13GPIO205R/W0hInput inversion control for this pin

Reset type: SYSRSn

12GPIO204R/W0hInput inversion control for this pin

Reset type: SYSRSn

11GPIO203R/W0hInput inversion control for this pin

Reset type: SYSRSn

10GPIO202R/W0hInput inversion control for this pin

Reset type: SYSRSn

9GPIO201R/W0hInput inversion control for this pin

Reset type: SYSRSn

8GPIO200R/W0hInput inversion control for this pin

Reset type: SYSRSn

7GPIO199R/W0hInput inversion control for this pin

Reset type: SYSRSn

6GPIO198R/W0hInput inversion control for this pin

Reset type: SYSRSn

5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

14.11.2.112 GPGODR Register (Offset = 192h) [Reset = 00000000h]

GPGODR is shown in Figure 14-116 and described in Table 14-125.

Return to the Summary Table.

GPIO G Open Drain Output Register (GPIO92 to 223)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-116 GPGODR Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-125 GPGODR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

30GPIO222R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

29GPIO221R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

28GPIO220R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

27GPIO219R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

26GPIO218R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

25GPIO217R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

24GPIO216R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

23GPIO215R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

22GPIO214R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

21GPIO213R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

20GPIO212R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

19GPIO211R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

18GPIO210R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO209R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16GPIO208R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

15GPIO207R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14GPIO206R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO205R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12GPIO204R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

11GPIO203R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

10GPIO202R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

9GPIO201R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

8GPIO200R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO199R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO198R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

14.11.2.113 GPGAMSEL Register (Offset = 194h) [Reset = 00000000h]

GPGAMSEL is shown in Figure 14-117 and described in Table 14-126.

Return to the Summary Table.

GPIO G Analog Mode Select register (GPIO192 to 223)

Selects between digital and analog functionality for GPIO pins.

0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t

Figure 14-117 GPGAMSEL Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-126 GPGAMSEL Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

30GPIO222R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

29GPIO221R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

28GPIO220R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

27GPIO219R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

26GPIO218R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

25GPIO217R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

24GPIO216R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

23GPIO215R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

22GPIO214R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

21GPIO213R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

20GPIO212R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

19GPIO211R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

18GPIO210R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

17GPIO209R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

16GPIO208R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

15GPIO207R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

14GPIO206R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

13GPIO205R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

12GPIO204R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

11GPIO203R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

10GPIO202R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

9GPIO201R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

8GPIO200R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

7GPIO199R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

6GPIO198R/W0hAnalog Mode select for this pin

Reset type: SYSRSn

5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

14.11.2.114 GPGGMUX1 Register (Offset = 1A0h) [Reset = 00000000h]

GPGGMUX1 is shown in Figure 14-118 and described in Table 14-127.

Return to the Summary Table.

GPIO G Peripheral Group Mux (GPIO192 to 207)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-118 GPGGMUX1 Register
3130292827262524
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO199GPIO198RESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-127 GPGGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO207R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO206R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO205R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO204R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO203R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO202R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO201R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO200R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO199R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO198R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

14.11.2.115 GPGGMUX2 Register (Offset = 1A2h) [Reset = 00000000h]

GPGGMUX2 is shown in Figure 14-119 and described in Table 14-128.

Return to the Summary Table.

GPIO G Peripheral Group Mux (GPIO208 to 223)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-119 GPGGMUX2 Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO215GPIO214GPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-128 GPGGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO223R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO222R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO221R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO220R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO219R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO218R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO217R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO216R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO215R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO214R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO213R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO212R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO211R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO210R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO209R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO208R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.116 GPGCSEL1 Register (Offset = 1A8h) [Reset = 00000000h]

GPGCSEL1 is shown in Figure 14-120 and described in Table 14-129.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-120 GPGCSEL1 Register
31302928272625242322212019181716
GPIO199GPIO198RESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-129 GPGCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO199R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO198R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

14.11.2.117 GPGCSEL2 Register (Offset = 1AAh) [Reset = 00000000h]

GPGCSEL2 is shown in Figure 14-121 and described in Table 14-130.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-121 GPGCSEL2 Register
31302928272625242322212019181716
GPIO207GPIO206GPIO205GPIO204
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-130 GPGCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO207R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO206R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO205R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO204R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO203R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO202R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO201R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO200R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.118 GPGCSEL3 Register (Offset = 1ACh) [Reset = 00000000h]

GPGCSEL3 is shown in Figure 14-122 and described in Table 14-131.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-122 GPGCSEL3 Register
31302928272625242322212019181716
GPIO215GPIO214GPIO213GPIO212
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-131 GPGCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO215R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO214R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO213R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO212R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO211R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO210R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO209R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO208R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.119 GPGCSEL4 Register (Offset = 1AEh) [Reset = 00000000h]

GPGCSEL4 is shown in Figure 14-123 and described in Table 14-132.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-123 GPGCSEL4 Register
31302928272625242322212019181716
GPIO223GPIO222GPIO221GPIO220
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-132 GPGCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO223R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO222R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO221R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO220R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO219R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO218R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO217R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO216R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.120 GPGLOCK Register (Offset = 1BCh) [Reset = 00000000h]

GPGLOCK is shown in Figure 14-124 and described in Table 14-133.

Return to the Summary Table.

GPIO G Lock Configuration Register (GPIO192 to 223)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-124 GPGLOCK Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-133 GPGLOCK Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

30GPIO222R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

29GPIO221R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

28GPIO220R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

27GPIO219R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

26GPIO218R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

25GPIO217R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

24GPIO216R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

23GPIO215R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

22GPIO214R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

21GPIO213R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

20GPIO212R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

19GPIO211R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

18GPIO210R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

17GPIO209R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

16GPIO208R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

15GPIO207R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

14GPIO206R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

13GPIO205R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

12GPIO204R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

11GPIO203R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

10GPIO202R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

9GPIO201R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

8GPIO200R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

7GPIO199R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

6GPIO198R/W0hConfiguration Lock bit for this pin

Reset type: SYSRSn

5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

14.11.2.121 GPGCR Register (Offset = 1BEh) [Reset = 00000000h]

GPGCR is shown in Figure 14-125 and described in Table 14-134.

Return to the Summary Table.

GPIO G Lock Commit Register (GPIO192 to 223)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-125 GPGCR Register
3130292827262524
GPIO223GPIO222GPIO221GPIO220GPIO219GPIO218GPIO217GPIO216
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
GPIO215GPIO214GPIO213GPIO212GPIO211GPIO210GPIO209GPIO208
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO207GPIO206GPIO205GPIO204GPIO203GPIO202GPIO201GPIO200
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO199GPIO198RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-134 GPGCR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO223R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

30GPIO222R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

29GPIO221R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

28GPIO220R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

27GPIO219R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

26GPIO218R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

25GPIO217R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

24GPIO216R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

23GPIO215R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

22GPIO214R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

21GPIO213R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

20GPIO212R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

19GPIO211R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

18GPIO210R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

17GPIO209R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

16GPIO208R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

15GPIO207R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

14GPIO206R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

13GPIO205R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

12GPIO204R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

11GPIO203R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

10GPIO202R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

9GPIO201R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

8GPIO200R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

7GPIO199R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

6GPIO198R/WSonce0hConfiguration lock commit bit for this pin

Reset type: SYSRSn

5RESERVEDR/WSonce0hReserved
4RESERVEDR/WSonce0hReserved
3RESERVEDR/WSonce0hReserved
2RESERVEDR/WSonce0hReserved
1RESERVEDR/WSonce0hReserved
0RESERVEDR/WSonce0hReserved

14.11.2.122 GPHCTRL Register (Offset = 1C0h) [Reset = 00000000h]

GPHCTRL is shown in Figure 14-126 and described in Table 14-135.

Return to the Summary Table.

GPIO H Qualification Sampling Period Control (GPIO224 to 255)

Figure 14-126 GPHCTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDQUALPRD2QUALPRD1QUALPRD0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-135 GPHCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/W0hReserved
23-16QUALPRD2R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/512

Reset type: SYSRSn

15-8QUALPRD1R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/511

Reset type: SYSRSn

7-0QUALPRD0R/W0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510

Reset type: SYSRSn

14.11.2.123 GPHQSEL1 Register (Offset = 1C2h) [Reset = 00000000h]

GPHQSEL1 is shown in Figure 14-127 and described in Table 14-136.

Return to the Summary Table.

GPIO H Qualifier Select 1 Register (GPIO224 to 239)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-127 GPHQSEL1 Register
3130292827262524
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-136 GPHQSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO239R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

29-28GPIO238R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

27-26GPIO237R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

25-24GPIO236R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

23-22GPIO235R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

21-20GPIO234R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

19-18GPIO233R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

17-16GPIO232R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

15-14GPIO231R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

13-12GPIO230R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

11-10GPIO229R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

9-8GPIO228R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

7-6GPIO227R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

5-4GPIO226R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO225R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO224R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.124 GPHQSEL2 Register (Offset = 1C4h) [Reset = 00000000h]

GPHQSEL2 is shown in Figure 14-128 and described in Table 14-137.

Return to the Summary Table.

GPIO H Qualifier Select 2 Register (GPIO240 to 255)

Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)

Figure 14-128 GPHQSEL2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-137 GPHQSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4GPIO242R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

3-2GPIO241R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

1-0GPIO240R/W0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)

Reset type: SYSRSn

14.11.2.125 GPHMUX1 Register (Offset = 1C6h) [Reset = 00000000h]

GPHMUX1 is shown in Figure 14-129 and described in Table 14-138.

Return to the Summary Table.

GPIO H Mux 1 Register (GPIO224 to 239)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-129 GPHMUX1 Register
3130292827262524
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-138 GPHMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO239R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO238R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO237R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO236R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO235R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO234R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO233R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO232R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO231R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO230R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO229R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO228R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO227R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO226R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO225R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO224R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.126 GPHMUX2 Register (Offset = 1C8h) [Reset = 00000000h]

GPHMUX2 is shown in Figure 14-130 and described in Table 14-139.

Return to the Summary Table.

GPIO H Mux 2 Register (GPIO240 to 255)

Defines pin-muxing selection for GPIO.

Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral selects being mapped to the GPIO. Refer to GPIO chapter for more details.

Figure 14-130 GPHMUX2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-139 GPHMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4GPIO242R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO241R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO240R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.127 GPHDIR Register (Offset = 1CAh) [Reset = 00000000h]

GPHDIR is shown in Figure 14-131 and described in Table 14-140.

Return to the Summary Table.

GPIO H Direction Register (GPIO224 to 255)

Controls direction of GPIO pins when the specified pin is configured in GPIO mode.

0: Configures pin as input.
1: Configures pin as output.

Reading the register returns the current value of the register setting.

Figure 14-131 GPHDIR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-140 GPHDIR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18GPIO242R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

17GPIO241R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

16GPIO240R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

15GPIO239R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14GPIO238R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

13GPIO237R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

12GPIO236R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

11GPIO235R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

10GPIO234R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

9GPIO233R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

8GPIO232R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

7GPIO231R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

6GPIO230R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

5GPIO229R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

4GPIO228R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

3GPIO227R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

2GPIO226R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

1GPIO225R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

0GPIO224R/W0hDefines direction for this pin in GPIO mode

Reset type: SYSRSn

14.11.2.128 GPHPUD Register (Offset = 1CCh) [Reset = FFFFFFFFh]

GPHPUD is shown in Figure 14-132 and described in Table 14-141.

Return to the Summary Table.

GPIO H Pull Up Disable Register (GPIO224 to 255)

Disables the Pull-Up on GPIO.

0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.

Figure 14-132 GPHPUD Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-141 GPHPUD Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W1hReserved
30RESERVEDR/W1hReserved
29RESERVEDR/W1hReserved
28RESERVEDR/W1hReserved
27RESERVEDR/W1hReserved
26RESERVEDR/W1hReserved
25RESERVEDR/W1hReserved
24RESERVEDR/W1hReserved
23RESERVEDR/W1hReserved
22RESERVEDR/W1hReserved
21RESERVEDR/W1hReserved
20RESERVEDR/W1hReserved
19RESERVEDR/W1hReserved
18GPIO242R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

17GPIO241R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

16GPIO240R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

15GPIO239R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

14GPIO238R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

13GPIO237R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

12GPIO236R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

11GPIO235R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

10GPIO234R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

9GPIO233R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

8GPIO232R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

7GPIO231R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

6GPIO230R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

5GPIO229R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

4GPIO228R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

3GPIO227R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

2GPIO226R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

1GPIO225R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

0GPIO224R/W1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.

Reading the register returns the current value of the register setting.

Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low. When coming out of reset, the pull-ups will remain disabled until the user enables them selectively in software by writing to this register.

Reset type: SYSRSn

14.11.2.129 GPHINV Register (Offset = 1D0h) [Reset = 00000000h]

GPHINV is shown in Figure 14-133 and described in Table 14-142.

Return to the Summary Table.

GPIO H Input Polarity Invert Registers (GPIO224 to 255)

Selects between non-inverted and inverted GPIO input to the device.

0: selects non-inverted GPIO input
1: selects inverted GPIO input

Reading the register returns the current value of the register setting.

Figure 14-133 GPHINV Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-142 GPHINV Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18GPIO242R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

17GPIO241R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

16GPIO240R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

15GPIO239R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

14GPIO238R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

13GPIO237R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

12GPIO236R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

11GPIO235R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

10GPIO234R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

9GPIO233R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

8GPIO232R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

7GPIO231R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

6GPIO230R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

5GPIO229R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

4GPIO228R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

3GPIO227R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

2GPIO226R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

1GPIO225R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

0GPIO224R/W0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input

Notes:
[1] Reading the register returns the current value of the register setting.

Reset type: SYSRSn

14.11.2.130 GPHODR Register (Offset = 1D2h) [Reset = 00000000h]

GPHODR is shown in Figure 14-134 and described in Table 14-143.

Return to the Summary Table.

GPIO H Open Drain Output Register (GPIO224 to GPIO255)

Selects between normal and open-drain output for the GPIO pin.

0: Normal Output
1: Open Drain Output

Reading the register returns the current value of the register setting.

Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes out on the on the PAD while a 1 value to be driven out tri-states the buffer.

Figure 14-134 GPHODR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-143 GPHODR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18GPIO242R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

17GPIO241R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

16GPIO240R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

15GPIO239R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14GPIO238R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

13GPIO237R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

12GPIO236R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

11GPIO235R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

10GPIO234R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

9GPIO233R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

8GPIO232R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

7GPIO231R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

6GPIO230R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

5GPIO229R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

4GPIO228R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

3GPIO227R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

2GPIO226R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

1GPIO225R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

0GPIO224R/W0hOutput Open-Drain control for this pin

Reset type: SYSRSn

14.11.2.131 GPHAMSEL Register (Offset = 1D4h) [Reset = FFFFFFFFh]

GPHAMSEL is shown in Figure 14-135 and described in Table 14-144.

Return to the Summary Table.

GPIO H Analog Mode Select register (GPIO224 to GPIO255)

Selects between digital and analog functionality for GPIO pins.

0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, t

Figure 14-135 GPHAMSEL Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 14-144 GPHAMSEL Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W1hReserved
30RESERVEDR/W1hReserved
29RESERVEDR/W1hReserved
28RESERVEDR/W1hReserved
27RESERVEDR/W1hReserved
26RESERVEDR/W1hReserved
25RESERVEDR/W1hReserved
24RESERVEDR/W1hReserved
23RESERVEDR/W1hReserved
22RESERVEDR/W1hReserved
21RESERVEDR/W1hReserved
20RESERVEDR/W1hReserved
19RESERVEDR/W1hReserved
18GPIO242R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

17GPIO241R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

16GPIO240R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

15GPIO239R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

14GPIO238R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

13GPIO237R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

12GPIO236R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

11GPIO235R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

10GPIO234R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

9GPIO233R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

8GPIO232R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

7GPIO231R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

6GPIO230R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

5GPIO229R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

4GPIO228R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

3GPIO227R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

2GPIO226R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

1GPIO225R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

0GPIO224R/W1h 0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions

Reading the register returns the current value of the register setting.

Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For all the IOs, the corresponding bits in these registers dont have any affect.

Reset type: SYSRSn

14.11.2.132 GPHGMUX1 Register (Offset = 1E0h) [Reset = 00000000h]

GPHGMUX1 is shown in Figure 14-136 and described in Table 14-145.

Return to the Summary Table.

GPIO H Peripheral Group Mux (GPIO224 to 239)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-136 GPHGMUX1 Register
3130292827262524
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-145 GPHGMUX1 Register Field Descriptions
BitFieldTypeResetDescription
31-30GPIO239R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

29-28GPIO238R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

27-26GPIO237R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

25-24GPIO236R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

23-22GPIO235R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

21-20GPIO234R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

19-18GPIO233R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

17-16GPIO232R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

15-14GPIO231R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

13-12GPIO230R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

11-10GPIO229R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

9-8GPIO228R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

7-6GPIO227R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

5-4GPIO226R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO225R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO224R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.133 GPHGMUX2 Register (Offset = 1E2h) [Reset = 00000000h]

GPHGMUX2 is shown in Figure 14-137 and described in Table 14-146.

Return to the Summary Table.

GPIO H Peripheral Group Mux (GPIO240 to 255)

Defines pin-muxing selection for GPIO.

Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.

Figure 14-137 GPHGMUX2 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-146 GPHGMUX2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0hReserved
29-28RESERVEDR/W0hReserved
27-26RESERVEDR/W0hReserved
25-24RESERVEDR/W0hReserved
23-22RESERVEDR/W0hReserved
21-20RESERVEDR/W0hReserved
19-18RESERVEDR/W0hReserved
17-16RESERVEDR/W0hReserved
15-14RESERVEDR/W0hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4GPIO242R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

3-2GPIO241R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

1-0GPIO240R/W0hDefines pin-muxing selection for GPIO

Reset type: SYSRSn

14.11.2.134 GPHCSEL1 Register (Offset = 1E8h) [Reset = 00000000h]

GPHCSEL1 is shown in Figure 14-138 and described in Table 14-147.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-138 GPHCSEL1 Register
31302928272625242322212019181716
GPIO231GPIO230GPIO229GPIO228
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-147 GPHCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO231R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO230R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO229R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO228R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO227R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO226R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO225R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO224R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.135 GPHCSEL2 Register (Offset = 1EAh) [Reset = 00000000h]

GPHCSEL2 is shown in Figure 14-139 and described in Table 14-148.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-139 GPHCSEL2 Register
31302928272625242322212019181716
GPIO239GPIO238GPIO237GPIO236
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-148 GPHCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-28GPIO239R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

27-24GPIO238R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

23-20GPIO237R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

19-16GPIO236R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

15-12GPIO235R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

11-8GPIO234R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO233R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO232R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.136 GPHCSEL3 Register (Offset = 1ECh) [Reset = 00000000h]

GPHCSEL3 is shown in Figure 14-140 and described in Table 14-149.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-140 GPHCSEL3 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-149 GPHCSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8GPIO242R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

7-4GPIO241R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

3-0GPIO240R/W0hSelects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

Reset type: SYSRSn

14.11.2.137 GPHCSEL4 Register (Offset = 1EEh) [Reset = 00000000h]

GPHCSEL4 is shown in Figure 14-141 and described in Table 14-150.

Return to the Summary Table.

Selects which controller's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin

0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
1000: CPU1.DMA1 selected
1001: CPU2.DMA1 selected

Figure 14-141 GPHCSEL4 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 14-150 GPHCSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0hReserved
27-24RESERVEDR/W0hReserved
23-20RESERVEDR/W0hReserved
19-16RESERVEDR/W0hReserved
15-12RESERVEDR/W0hReserved
11-8RESERVEDR/W0hReserved
7-4RESERVEDR/W0hReserved
3-0RESERVEDR/W0hReserved

14.11.2.138 GPHLOCK Register (Offset = 1FCh) [Reset = 00000000h]

GPHLOCK is shown in Figure 14-142 and described in Table 14-151.

Return to the Summary Table.

GPIO H Lock Configuration Register (GPIO224 to 255)

GPIO Configuration Lock for GPIO.

0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin

Figure 14-142 GPHLOCK Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 14-151 GPHLOCK Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18GPIO242R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

17GPIO241R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

16GPIO240R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

15GPIO239R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

14GPIO238R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

13GPIO237R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

12GPIO236R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

11GPIO235R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

10GPIO234R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

9GPIO233R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

8GPIO232R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

7GPIO231R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

6GPIO230R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

5GPIO229R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

4GPIO228R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

3GPIO227R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

2GPIO226R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

1GPIO225R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

0GPIO224R/W0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register which control the same pin can be changed

Reset type: SYSRSn

14.11.2.139 GPHCR Register (Offset = 1FEh) [Reset = 00000000h]

GPHCR is shown in Figure 14-143 and described in Table 14-152.

Return to the Summary Table.

GPIO H Lock Commit Register (GPIO224 to 255)

GPIO Configuration Lock Commit for GPIO:

1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Figure 14-143 GPHCR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO242GPIO241GPIO240
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
GPIO239GPIO238GPIO237GPIO236GPIO235GPIO234GPIO233GPIO232
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
GPIO231GPIO230GPIO229GPIO228GPIO227GPIO226GPIO225GPIO224
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 14-152 GPHCR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WSonce0hReserved
30RESERVEDR/WSonce0hReserved
29RESERVEDR/WSonce0hReserved
28RESERVEDR/WSonce0hReserved
27RESERVEDR/WSonce0hReserved
26RESERVEDR/WSonce0hReserved
25RESERVEDR/WSonce0hReserved
24RESERVEDR/WSonce0hReserved
23RESERVEDR/WSonce0hReserved
22RESERVEDR/WSonce0hReserved
21RESERVEDR/WSonce0hReserved
20RESERVEDR/WSonce0hReserved
19RESERVEDR/WSonce0hReserved
18GPIO242R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

17GPIO241R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

16GPIO240R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

15GPIO239R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

14GPIO238R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

13GPIO237R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

12GPIO236R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

11GPIO235R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

10GPIO234R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

9GPIO233R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

8GPIO232R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

7GPIO231R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

6GPIO230R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

5GPIO229R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

4GPIO228R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

3GPIO227R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

2GPIO226R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

1GPIO225R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn

0GPIO224R/WSonce0h 1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed

Reset type: SYSRSn