SPRZ445A February 2018 – October 2026 DRA790 , DRA791 , DRA793 , DRA797
Delay Needed to Read Some Timer Registers After Wakeup
Medium
For GP timers:
If a General Purpose Timer (GPTimer) is in posted mode (TSICR[2] POSTED=1), due to internal resynchronizations, values read in TCRR, TCAR1 and TCAR2 registers right after the timer interface clock (L4) goes from stopped to active may not return the expected values. The most common event leading to this situation occurs upon wake up from idle.
GP Timer non-posted synchronization mode is not impacted by this limitation.
For watchdog timers:
Due to internal resynchronizations, values read in Watchdog timers WCRR registers right after the timer interface clock (L4) goes from stopped to active may not return the expected values. The most common event leading to this situation occurs upon wake up from idle. All watchdog timers support only POSTED internal synchronization mode. There is no capability to change the internal synchronization scheme to NON-POSTED by software.
For GP timers:
For reliable counter read upon wakeup from IDLE state, software need to issue a non posted read to get accurate value.
To get this non posted read, TSICR[2] POSTED needs to be set at '0' and TSICR[3] READ_MODE needs to be set at '1'.
Note: For GP Timers 1/2/10 the TSICR[3] READ_MODE is a write only bit and reads to this register always return 0.
For watchdog timers:
Software has to wait at least (2 timer interface clock cycles + 1 timer functional clock cycle) after L4 clock wakeup before reading WCRR register of the Watchdog timers.
SR 2.1, 2.0
DRA79x: 2.1, 2.0
TDA2Ex (23mm): 2.0, 1.0
TDA2Ex (17mm): 2.1, 2.0
AM571x: 2.1, 2.0, 1.0
AM570x: 2.1, 2.0
DRA72x: 2.0, 1.0
DRA71x: 2.1, 2.0