SPRZ445A February   2018  – October 2026 DRA790 , DRA791 , DRA793 , DRA797

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 2.1, 2.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i709
    9.     i727
    10.     i729
    11.     i734
    12.     i767
    13.     i802
    14.     i803
    15.     i810
    16.     i813
    17.     i814
    18.     i815
    19.     i819
    20.     i820
    21.     i824
    22.     i829
    23.     i834
    24.     i849
    25.     i862
    26.     i863
    27.     i869
    28.     i870
    29.     i871
    30.     i872
    31.     i874
    32.     i878
    33.     i879
    34.     i883
    35.     i887
    36.     i889
    37.     i890
    38.     i893
    39.     i895
    40.     i896
    41.     i897
    42.     i898
    43.     i899
    44.     i900
    45.     i903
    46.     i904
    47.     i916
    48.     i927
    49.     i928
    50.     i929
    51.     i930
    52.     i932
    53.     i933
    54.     i940
    55.     i2446
    56.     i2452
  4. 3Silicon Limitations
    1.     Revisions SR 2.1, 2.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i876
    10.     i877
    11.     i892
    12.     i909
  5. 4Silicon Cautions
    1.     Revisions SR 2.1, 2.0 - Cautions List
    2.     i781
    3. 4.1 79
    4.     i827
    5.     i832
    6.     i836
    7.     i839
    8.     i864
    9.     i885
    10.     i886
    11.     i912
    12.     i918
    13.     i926
    14.     i931
    15.     i934
    16. 4.2 92
  6. 5Revision History

i803

MMCHS Read Transfer with CMD23 Never Complete When BCE=0 And ADMA Used

CRITICALITY

Low

DESCRIPTION

A data time-out (DTO) error interrupt (MMCHS_STAT[20] DTO=0x1) occurs at the end of reading transfer with CMD23. In this case, transfer completed (TC) interrupt (MMCHS_STAT[1] TC=0x1) never occurs.

This bugs appears only with following restrictive conditions:

  • Use CMD23 (command used to specify number of reading and writing block)
  • Block count enable BCE (MMCHS_CMD[1] = 0x0
  • ADMA (integrated controller DMA system engine) used
  • Reading transfer (writing transfer is not affected)
  • Only finite transfer affected. CMD12 (stop infinite transfer command) command are not affected.
  • Issue happens with both large block count (>2^16) and small block count (<=2^16)

Note: These conditions are used typically with UHS SD cards with 32-bit-wide CMD23 capability.

If software is modified to skip TC occurrence and proceed with data comparison, it appears that all data was received correctly.

WORKAROUND

If the card is configured to send one more block (through the CMD23 argument) compared to what is configured in the host, then the Read transfer completes correctly (in this case, no DTO, TC occurs and data is correct).

REVISIONS IMPACTED

SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0