DRA797

ACTIVE

800 MHz Arm Cortex-A15 SoC processor w/ 750 MHz C66x DSP for audio amplifier

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Product details

Parameters

Arm CPU 1 ARM Cortex-A15 Arm MHz (Max.) 800 DSP 1 C66x DSP MHz (Max) 750 DRAM DDR3-1333, DDR3L-1333 Co-processor(s) 2 Dual ARM Cortex-M4 Hardware accelerators 2 Viterbi Decoder, 1 Audio Tracking Logic EMIF 1 32-bit CSI-2 2 DL Other on-chip memory 512 KB Ethernet MAC 10/100/1000, 2-port 1Gb switch Parallel video input ports 4 Display type 1 HDMI OUT, 2 LCD OUT Serial I/O CAN, I2C, SPI, UART, USB Storage interface 1x SDIO 4b, 1x SDIO 8b, 1x UHSI 4b, 1x eMMC 8b PCIe 2 PCIe Gen2 McASP 8 USB 1 USB3.0, 2 USB2.0 open-in-new Find other DRAx digital cockpit SoCs

Features

  • Architecture designed for infotainment co-processor applications, hybrid radio and amplifier applications
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® Interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)

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Description

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA79x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA79x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA79x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.

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More Information

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet DRA79x Infotainment Applications Processor datasheet (Rev. F) Nov. 25, 2019
* Errata DRA79x Silicon Errata Dec. 12, 2016
Application notes AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) Jan. 06, 2020
Application notes Integrating New Cameras With Video Input Port on DRA7xx SoCs Jun. 11, 2019
User guides DRA79x J6 RSP - SoC for Automotive Infotainment Technical Reference Manual (Rev. C) May 21, 2019
User guides DRA79x EVM CPU board user's guide (Rev. B) Mar. 11, 2019
Application notes Achieving Early CAN Response on DRA7xx Devices Nov. 28, 2018
Application notes DRA74x_75x/DRA72x Performance (Rev. A) Oct. 31, 2018
Application notes Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices Sep. 14, 2018
Application notes The Implementation of YUV422 Output for SRV Aug. 02, 2018
Application notes MMC DLL Tuning (Rev. B) Jul. 31, 2018
Application notes Integrating AUTOSAR on TI SoC: Fundamentals Jun. 18, 2018
Application notes ECC/EDC on TDAxx (Rev. B) Jun. 13, 2018
Application notes Tools and Techniques to Root Case Failures in Video Capture Subsystem Jun. 12, 2018
Application notes Sharing VPE Between VISIONSDK and PSDKLA May 04, 2018
Technical articles Smart sensors are going to change how you drive (because eventually, you won’t) Apr. 25, 2018
Application notes Android Boot Optimization on DRA7xx Devices (Rev. A) Feb. 13, 2018
Technical articles AI in Automotive: Practical deep learning Feb. 08, 2018
Technical articles How to maintain automotive front camera thermal performance on a hot summer day Feb. 02, 2018
Technical articles Development platforms pave the way to production systems for ADAS Jan. 19, 2018
Application notes Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) Nov. 30, 2017
Application notes Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) Nov. 27, 2017
Application notes Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) Nov. 07, 2017
Application notes A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) Nov. 03, 2017
Application notes Optimization of GPU-Based Surround View on TI’s TDA2x SoC Sep. 12, 2017
Application notes Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices Aug. 14, 2017
Application notes Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices Jul. 12, 2017
Application notes Linux Boot Time Optimizations on DRA7xx Devices Mar. 31, 2017
Application notes Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) Feb. 17, 2017
Application notes Early Splash Screen on DRA7x Devices Jan. 31, 2017
Application notes Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) Dec. 15, 2016
Application notes Gstreamer Migration Guidelines Apr. 26, 2016
User guides Jacinto6 Android Video Decoder Software Design Specification User's Guide Apr. 21, 2016
User guides Jacinto6 Android Video Encoder Software Design Specification User's Guide Apr. 21, 2016
Application notes Flashing Binaries to DRA7xx Factory Boards Using DFU Apr. 14, 2016
Application notes Tools and Techniques for Audio Debugging Apr. 13, 2016
Application notes Debugging Tools and Techniques With IPC3.x Mar. 30, 2016
Application notes Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) Jan. 15, 2016
White papers Informational ADAS as Software Upgrade to Today’s Infotainment Systems Oct. 14, 2014
Application notes Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device Aug. 13, 2014
White papers Today’s high-end infotainment soon becoming mainstream Jun. 02, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The Jacinto™ DRA79x evaluation module designed to speed up development efforts and reduce time-to-market for applications such as infotainment, reconfigurable digital cluster, or integrated digital cockpit. To allow scalability and reuse across Jacinto DRA79x Infotainment SoCs, the EVM is (...)

Features

Hardware

  • DRA79x Processor
  • 2GB DDR3L
  • LP8733/LP8732 Power Management ICs
  • 4 GB eMMC
  • 10.1" 1280X800 Capacitive Touch Screen LCD option
  • JAMR3 tuner board

Software

  • Linux
  • Android
  • StarterWare

Connectivity

  • Gigabit Ethernet (2)
  • PCIe
  • e/mSATA
  • Micro SD Card
  • Micro USB 2.0
  • USB 3.0
  • HDMI
  • Audio in/out
  • WiLink8 Q (Connector

Software development

SOFTWARE DEVELOPMENT KITS (SDK) Download
Processor Software Development Kit for DRA7x Jacinto™ Processors – Linux, Android, and RTOS
PROCESSOR-SDK-DRA7X Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Features
Processor SDK Linux Automotive features
  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • 3D graphics support
  • 2D graphics support
  • Integrated WLAN and Bluetooth® support
  • GUI-based application launcher
  • Example applications, including:
    • ARM benchmarks: Dhrystone, Linpack (...)
DEBUG PROBES Download
XDS110 JTAG Debug Probe
TMDSEMU110-U The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all ARM and (...)
99
Features

The XDS110 is the latest entry level debug probe (emulators) for TI embedded processors. Designed to be a complete solution that delivers JTAG and SWD connectivity at a low cost, the XDS110 is the debug probe of choice for entry-level debugging of TI microcontrollers, processors and SimpleLink (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM695A.ZIP (15 KB) - BSDL Model
SIMULATION MODELS Download
SPRM696.ZIP (2 KB) - Thermal Model
SIMULATION MODELS Download
SPRM697.ZIP (9618 KB) - IBIS Model
CALCULATION TOOLS Download
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
FCBGA (CBD) 538 View options

Ordering & quality

Support & training

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