SPRZ491E December   2020  – December 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0, 2.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0, 2.0 Usage Notes
    2. 3.2 Silicon Revision 1.0, 2.0 Advisories
    3.     i2049
    4.     i2062
    5.     i2091
    6.     i2103
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    9. 3.3 i2126
    10. 3.4 i2127
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    14. 3.5 i2151
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    18.     i2161
    19.     i2163
    20.     i2166
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    35.     i2209
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    47.     i2241
    48.     i2242
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    50.     i2244
    51.     i2245
    52.     i2246
    53.     i2249
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    85.     i2424
    86.     i2435
    87.     i2459
  5.   Trademarks
  6.   Revision History

i2246

PCIe: Automatic compliance entry fails when unused SERDES lanes are not assigned to PCIe Controller

Details

PCIe fails to enter compliance state when connected to a passive load. This happens when unused SERDES lanes are not assigned to PCIe Controller. For example, if PCIe is configured in 1 lane mode, then compliance entry fails if only lane 0 of SERDES is assigned to PCIe Controller and lanes 1, 2, and 3 are not assigned to PCIe Controller.

Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, Controller sees unused lanes to be out of electrical idle (indicating that the lane is not connected to passive load) and this prevents compliance entry.

Please note that this issue only affects automatic compliance entry mechanism when connected to passive load (for example a scope that presents termination in its receive lines but does not bring its transmit lines out of electrical idle). This issue does not affect Enter Compliance or Compliance Receive mechanisms defined by PCIe specification.

Workaround

Only available workaround is to assign all SERDES lanes to PCIe during compliance validation.