SPRZ545D July   2023  – April 2025 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   TMS320F28P65x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts with Repeat Block
      3. 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only
      4. 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.1 Advisory
      5.      Advisory
      6. 3.2.2 Advisory
      7. 3.2.3 Advisory
      8. 3.2.4 Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14. 3.2.5 Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1. 4.2.1 Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

3.2.3 Advisory

ePWM: ePWM TZFRC and TZCLR Events May be Missed When PERCLKDIVSEL.EPWMCLKDIV = 1

Revisions Affected

0, A

Details

The TZFRC bit is used for software-forced trip events, while the TZCLR bit is used for clearing the trip-zone events. On devices with EPWMCLKDIV, the TZFRC and TZCLR write may be missed and leave the output unaffected if PERCLKDIVSEL.EPWMCLKDIV is programmed to 1. This bit is programmed to 1 by default (EPWMCLK is PLLSYSCLK/2).

Workarounds

  1. Configure EPWMCLK = PLLSYSCLK (PERCLKDIVSEL.EPWMCLKDIV = 0).
  2. If the user has to configure EPWMCLK = PLLSYSCLK/2 (PERCLKDIVSEL.EPWMCLKDIV = 1), select one of the reserved mux inputs of EPWMXBAR to be used for the trip using the following driverlib software sequence.

    EPWMXBAR → Digital Compare → Trip Zone

Initialization

  1. Configure both trip zone actions for Digital Compare Output A Event 1 or 2 on EPWMxA and Digital Compare Output B Event 1 or 2 on EPWMxB.
    • EPWM_setTripZoneAction()
  2. Configure the input signals for TRIPIN1–15 or the ORed Combinational logic of TRIPIN1–15.
    • EPWM_selectDigitalCompareTripInput()
  3. Configure the Digital Compare condition for DCAEVT1/2 and DCBEVT1/2.
    • EPWM_ setTripZoneDigitalCompareEventCondition()
  4. Select the EPWMXBAR Mux Input as Reserved to the Digital Compare Submodule.
    • XBAR_setEPWMMuxConfig()
    • XBAR_enableEPWMMux()

Application Code

To Trip the PWMs, you can invert the EPWMXBAR state using XBAR_invertEPWMSignal().