SPRZ545D July   2023  – April 2025 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   TMS320F28P65x MCUs Silicon Errata Silicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts with Repeat Block
      3. 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only
      4. 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.1 Advisory
      5.      Advisory
      6. 3.2.2 Advisory
      7. 3.2.3 Advisory
      8. 3.2.4 Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14. 3.2.5 Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1. 4.2.1 Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

1.1 Usage Notes Matrix

Table 1-1 Usage Notes Matrix
NUMBER TITLE SILICON REVISIONS AFFECTED
0 A
Section 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Yes Yes
Section 3.1.2 Caution While Using Nested Interrupts with Repeat Block Yes Yes
Section 3.1.3 GPIO: GPIO Data Register is Reset by CPU1 Reset Only Yes Yes
Section 3.1.4 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature Yes Yes