Details:

During OSPI boot mode, including fallback modes that would result in OSPI boot mode, ROM configures pin GPIO61 as OSPI0_RESET_OUT0. If this pin is connected to the Reset pin of the OSPI Flash Memory, boot failures may occur due to a reset signal management issue in the OSPI controller.

During OSPI boot mode, the ROM code:

1. Configures GPIO61 in OSPI0_RESET_OUT0 mux mode
2. Correctly asserts the reset signal (drives low)
3. Fails to de-assert the reset signal due to incorrect OSPI controller configuration (GPIO61 pin remains driven low)

If GPIO61 is connected to the Flash Memory Reset pin, the flash device remains in reset state. This prevents proper boot sequence completion. This issue affects all package types where GPIO61 is utilized for OSPI Flash reset control.

Workaround(s):

Option 1: Do not use GPIO61 pin to reset the flash. Use PORz/WARMRSTn to reset the flash device on a power cycle and use another GPIO for OSPI0_REST_OUT0 and pass that signal through an AND gate with PORz/WARMRSTn. See AM261x OSPI Reset using any OSPI0_RESET_OUT0 pin AND PORz/WARMRSTn for an example.

Option 2: Gate GPIO61 to prevent propagation to the reset logic during boot, then AND that signal with PORz/WARMRSTn to use as a reset during power cycles for the flash device. One example implementation is shown in AM261x OSPI Reset using Gated GPIO61 pin AND PORz/WARMRSTn.