SPVA068 July   2026 ADC3548 , ADC3549 , ADC3568 , ADC3569 , ADC3648 , ADC3649 , ADC3668 , ADC3669

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2ADC366x Internal Rx Architecture
    1. 2.1 1.4GHz Wideband, High Performance and Low Power Direct RF Sampling
    2. 2.2 Integrated Digital Downconverter (DDC) and 32-Bit NCO
  6. 3 ADC366x Low Latency Mode
  7. 4IFF Pulse Processing Performance
    1. 4.1 ADC3669 Performance in Presence of a High-Power Signal Pulse
    2. 4.2 ADC3669 Performance in Presence of a Weak Signal Pulse
  8. 5Summary - Buying Back Time
  9. 6References

2.2 Integrated Digital Downconverter (DDC) and 32-Bit NCO

The ADC366x provides up to four Digital Downconverters (DDC) paired with 32-bit Numerically Controlled Oscillators (NCO).

Unlike analog systems which are susceptible to thermal drifts, the digital NCO allows to digitally shift the 1030MHz signal down to baseband within the ADC itself while, maintaining excellent stability across temperature. This ensures that the internal pulse-detection algorithms receive a consistent signal, preventing timing walk or jitter which helps maintain better range accuracy.

Internal Rx Architecture of ADC3668/ADC3669 Figure 2-2 Internal Rx Architecture of ADC3668/ADC3669

As illustrated in Figure 2-3, leveraging the ADC366x’s internal NCO and decimation blocks optimizes frequency planning by eliminating alias images at the hardware level. Performing decimation-by-4 natively within the ADC provides an expected 6dB processing gain by filtering out-of-band quantization noise. Offloading this digital down-conversion task from the FPGA to the converter helps minimize the power consumption by saving FPGA logic resources and reducing interface bandwidth.

Complex FFT output with internal DDC + NCO and Decimation-by-4 Figure 2-3 Complex FFT output with internal DDC + NCO and Decimation-by-4