SSDA010 Subsystem design

SSDA010 August 2025 MSPM0G3507

7.1 Application Code – Cascaded Signal Computation

A key part of this subsystem's functionality is computing the fully cascaded signal output, represented as G1 × G2 × V_in. This is handled in the cascade_input_voltage() function, which reconstructs the total amplified input by accounting for both op amp stages and the bias voltages applied through DACs.

Figure 7-2 Cascade_Input_Voltage() Code

The mathematical model behind the computation is:

Equation 1.

(G 1 \times G 2 \times V_{i n} 1) = V_{o u t} 2 + ((1 + G 1) \times G 2 \times V_{d a c} 1) \times 2^{4} - ((1 + G 2) \times V_{d a c} 2 \times 2^{4}

Derived from the combination of

Equation 2.

V_{o u t} 1 = - G 1 \times V_{i n} 1 + (1 + G 1) \times V_{d a c} 1

Equation 3.

V_{o u t} 2 = - G 2 \times V_{o u t} 1 + (1 + G 2) \times V_{d a c} 2

Where:

G1 and G2 are the gains of the first and second op amp stages.
Vout1 and Vout2 are the outputs of the first and second-stage amplifiers (OPA0 and OPA1).
Vdac1 and Vdac2 are the bias voltages applied to OPA0 and OPA1 respectively through DAC8_0 and DAC8_1.

This equation compensates for the effects of both DAC-induced offsets in each stage and reconstructs the true input signal as if no offset biasing had occurred. The use of a left shift (<< 4) in the code accounts for the 8-bit DAC's limited resolution when scaled back to a 12-bit context, as each DAC value must be multiplied by 16 (for example, 2⁴) to align with the full ADC range. This reconstructed signal is then transmitted via UART, providing the host system with a DC-compensated representation of the original input voltage, scaled by the configured system gains