SSDA010 August   2025 MSPM0G3507

 

  1.   1
  2. 1Description
  3. 2Required Peripherals
  4. 3Design Steps
  5. 4Design Considerations
  6. 5Software Flow Chart
  7. 6Device Configuration
  8. 7Application Code
    1. 7.1 Application Code – Cascaded Signal Computation
  9. 8Results
  10. 9Additional Resources
  11.   Trademarks

7 Application Code

The main loop runs a self-compensating sequence that includes DC bias adjustment, cascaded voltage calculation, saturation control, and UART transmission.

MSPM0G3507 Main.c code Figure 7-1 Main.c code
  • remove_dc_voltage() calculates the amplified input using the output of the first op amp and DAC reference. An exponential moving average (EMA) filter isolates the DC component, and the DAC is adjusted to center the output voltage around mid-scale.
  • cascade_input_voltage() computes the cascaded signal G1⋅G2⋅Vin using both DAC values and op amp outputs. This output represents the system's filtered and gain-corrected signal.
  • saturation_control() prevents output clipping in the second op amp by adjusting the DAC reference if the output voltage exceeds defined limits.
  • send_UART_Data() breaks the 32-bit cascaded output into 4 bytes and transmits over UART.
  • Timer and ADC interrupts control periodic execution and sampling. The TIMERA ISR sets a timeout flag every 50 ms, while ADC ISRs capture and store conversion results.

All tunable system constants such as gain values, voltage thresholds, buffer length, and smoothing factor are defined in customizable_features.h.