6 Device Configuration

This subsystem utilizes TI's SysConfig graphical tool to configure all necessary peripherals. As shown in Figure Figure 6-1, the MSPM0 device internally routes the input signal through two cascaded op amp stages (OPA0 and OPA1), each configured as an inverting amplifier with programmable gain using internal resistor ladder taps (RTOP and RBOT). DAC8_0 and DAC8_1 provide biasing voltages to the non-inverting inputs of OPA0 and OPA1 respectively, enabling dynamic DC offset control at each stage.

The outputs of the op amps are monitored by ADC channels ADC0.13 and ADC1.13. TIMERX is configured to generate periodic interrupts that regulate the signal sampling rate, maintaining stable compensation over time. UART is also configured for serial communication over the backchannel interface, transmitting the cascaded output as a fixed 4-byte data packet.

All critical parameters—such as gain values, saturation limits, and filter constants—are defined in customizable_features.h to allow easy tuning without altering the core application logic.