STDA062 October   2026 TDA4VH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2SoC Architecture
    1. 2.1 Vector DSP and Matrix Math Compute Cluster
    2. 2.2 Vision and Motion Processing Accelerators
    3. 2.3 ARM® Cortex®-A72 CPU Cores
    4. 2.4 ARM Cortex-R5F CPU Cores
    5. 2.5 On-Chip Memory and High-Performance Interfaces
    6. 2.6 Package and Power Consumption
  6. 3Machine Learning Software Development Tools
    1. 3.1 TI Deep Learning Tools
    2. 3.2 TI Edge AI Studio
  7. 4TDAx Family Scalability
  8. 5Conclusion
  9. 6References

4 TDAx Family Scalability

The TDA4VH-Q1 described in this paper represents the highest-integration member of TI's TDA4x processor family. The family spans a range of production-ready options with varying compute performance and power envelopes, enabling drone designers to select the appropriate device for their platform class without rewriting application software. The Processor SDK and TIDL tool chain are common across the family, so software developed on one device can be redeployed on another with minimal modification. Furthermore, the TDA5 next-gen devices further enhance performance and IP integration. Table 4-1 summarizes the key parameters across select members of the TDAx family.

Table 4-1 TDAx Family Scalability
Processor Family Member Application Cores (MPU) Deep Learning (C7x DSP / MMA) On-Chip and External Memory Interfaces
TDA4VM-Q1 2x Arm Cortex-A72 1x C7x DSP + MMA 8MBytes L3 + 1x LPDDR4
TDA4VE-Q1 2x Arm Cortex-A72 2x C7x DSP + MMA 4MBytes L3 + 2x LPDDR4
TDA4VH-Q1 8x Arm Cortex-A72 4x C7x DSP + MMA 8MBytes L3 + 4x LPDDR4
TDA54-Q1 (Next Gen) 8x Arm Cortex-A720AE 4x C7 Neural Processing Units (Up to 400TOPS) 24MBytes L3 + 4 LPDDR4/5x

This scalability provides a practical advantage for drone manufacturers developing a product family across payload classes - from a lightweight fixed-wing surveillance platform to a heavy-lift cargo UAS - where a unified AI software stack must run on processors with varying performance and power envelopes. Furthermore, the common toolchain also enables algorithm development and validation to begin on higher-performance devices before final optimization for the target platform.