SWRA689 February   2022 AWR6843 , AWR6843AOP , IWR6843 , IWR6843AOP

 

  1.   Trademarks
  2. 1Introduction
  3. 2Radar System Overview
    1. 2.1 Architecture Overview
    2. 2.2 Equipment for Evaluation
      1. 2.2.1 Hardware
      2. 2.2.2 Software
    3. 2.3 Radar Measurement Cycle
  4. 3Active Mode Optimizations
    1. 3.1 Acquisition Period Overview
    2. 3.2 Acquisition Period Optimization Parameters
    3. 3.3 Acquisition Period Optimization Tradeoffs
    4. 3.4 Acquisition Period Optimization Implementation
      1. 3.4.1 Single Chirp Duration
      2. 3.4.2 Number of Chirps
      3. 3.4.3 Number of Tx Antennas
  5. 4Idle Mode Optimizations
    1. 4.1 Inter-Frame Period Overview
    2. 4.2 Idle Mode Techniques
      1. 4.2.1 Power Domain Components
        1. 4.2.1.1 DSP Power Domain Shutdown
      2. 4.2.2 Digital Domain Components
        1. 4.2.2.1 DSS Clock Gating (DSP Subsystem)
        2. 4.2.2.2 MSS VCLK to 40 MHz (Master Subsystem)
        3. 4.2.2.3 BSS Clock Gating (Radar Subsystem - BIST)
      3. 4.2.3 Analog Domain Components
        1. 4.2.3.1 RF Power Down (Radar Subsystem - Analog Front End)
        2. 4.2.3.2 APLL Power Down (Radar Subsystem - APLL)
      4. 4.2.4 Component Summary
    3. 4.3 Idle Mode Implementation
      1. 4.3.1 Idle Power CLI Configuration in 68xx Low-Power Demo
      2. 4.3.2 Example Invoking Idle Mode
        1. 4.3.2.1 Nominal Power Down Scheme
        2. 4.3.2.2 Full Power Down Scheme
        3. 4.3.2.3 Fast Power Down Scheme (Clock Gates Only)
  6. 5Power Measurement Methods and Results
    1. 5.1 Power Measurement Method
    2. 5.2 Idle Mode Power Measurements
      1. 5.2.1 Nominal Power Down Scheme Measurements
      2. 5.2.2 Full Power Down Scheme Measurements
      3. 5.2.3 Fast Power Down Scheme Measurements
  7. 6References

4.3.1 Idle Power CLI Configuration in 68xx Low-Power Demo

The CLI commands idlePowerDown and idlePowerCycle are implemented to invoke any combination of the Idle Mode components as specified by the user.

  • idlePowerDown – Will invoke each of the specified Idle Mode functions as specified by the user and leaves the device in an idle state indefinitely. A full device reset is required to return to a functional state.
  • idlePowerCycle -- Will invoke each of the specified Idle Mode functions as specified by the user and then return to a functional state after a user specified delay.

Both of the commands use the following parameter structure <subframeidx> <enDSPpowerdown> <enDSSclkgate> <enMSSvclkgate> <enBSSclkgate> <enRFpowerdown> <enAPLLpowerdown> <enAPLLGPADCpowerdown> <componentMicroDelay> <idleModeMicroDelay>, where:

  • <subframeidx>: always set to -1
  • <enDSPpowerdown>: 1 enables DSP Power Domain Off, 0 disables
  • <enDSSclkgate>: 1 enables DSS Clock Gating, 0 disables
  • <enMSSvclkgate>: 1 enables MSS Clock Gating, 0 disables
  • <enBSSclkgate>: 1 enables BSS Clock Gating, 0 disables (Note: Performed last at code level as discussed above)
  • <enRFpowerdown>: 1 enables RF Power Down, 0 disables
  • <enAPLLpowerdown>: 1 enables APLL Power Down, 0 disables
  • <enAPLLGPADCpowerdown>: 1 enables APLL/GPADC Power Down, 0 disables
  • <componentMicroDelay>: specifies a delay duration, in microseconds, between each successive power function
  • <idleModeMicroDelay>: specifies a delay duration, in microseconds, after Idle Mode has been acheived but before device is powered up (if using idlePowerCycle)