SWRA689 February   2022 AWR6843 , AWR6843AOP , IWR6843 , IWR6843AOP

 

  1.   Trademarks
  2. 1Introduction
  3. 2Radar System Overview
    1. 2.1 Architecture Overview
    2. 2.2 Equipment for Evaluation
      1. 2.2.1 Hardware
      2. 2.2.2 Software
    3. 2.3 Radar Measurement Cycle
  4. 3Active Mode Optimizations
    1. 3.1 Acquisition Period Overview
    2. 3.2 Acquisition Period Optimization Parameters
    3. 3.3 Acquisition Period Optimization Tradeoffs
    4. 3.4 Acquisition Period Optimization Implementation
      1. 3.4.1 Single Chirp Duration
      2. 3.4.2 Number of Chirps
      3. 3.4.3 Number of Tx Antennas
  5. 4Idle Mode Optimizations
    1. 4.1 Inter-Frame Period Overview
    2. 4.2 Idle Mode Techniques
      1. 4.2.1 Power Domain Components
        1. 4.2.1.1 DSP Power Domain Shutdown
      2. 4.2.2 Digital Domain Components
        1. 4.2.2.1 DSS Clock Gating (DSP Subsystem)
        2. 4.2.2.2 MSS VCLK to 40 MHz (Master Subsystem)
        3. 4.2.2.3 BSS Clock Gating (Radar Subsystem - BIST)
      3. 4.2.3 Analog Domain Components
        1. 4.2.3.1 RF Power Down (Radar Subsystem - Analog Front End)
        2. 4.2.3.2 APLL Power Down (Radar Subsystem - APLL)
      4. 4.2.4 Component Summary
    3. 4.3 Idle Mode Implementation
      1. 4.3.1 Idle Power CLI Configuration in 68xx Low-Power Demo
      2. 4.3.2 Example Invoking Idle Mode
        1. 4.3.2.1 Nominal Power Down Scheme
        2. 4.3.2.2 Full Power Down Scheme
        3. 4.3.2.3 Fast Power Down Scheme (Clock Gates Only)
  6. 5Power Measurement Methods and Results
    1. 5.1 Power Measurement Method
    2. 5.2 Idle Mode Power Measurements
      1. 5.2.1 Nominal Power Down Scheme Measurements
      2. 5.2.2 Full Power Down Scheme Measurements
      3. 5.2.3 Fast Power Down Scheme Measurements
  7. 6References

4.3.2.3 Fast Power Down Scheme (Clock Gates Only)

idlePowerCycle -1 0 1 1 1 0 0 0 0 1

This scheme first performs the below power down functions, waits 1 µs, and then performs power up in reverse order:

  • DSS Clock Gate
  • MSS VCLK to 40 MHz
  • BSS Clock Gate

This scheme is designed to showcase an Idle State where very fast switching is needed. Because of this none of the Analog Domain components are leveraged. An example use case where this scheme could be used is between frames in operational mode where a fast framing time is used.