SWRS314C January   2024  – October 2026 AWR2544

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions - Digital
    4. 6.4 Signal Descriptions - Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1 QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements#GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C#GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics#GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-64#GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-65
      2. 7.12.2 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)#GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-236#GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-237#GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)#GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-244#GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-245#GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)#GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-70#GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-71#GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-73
      3. 7.12.3 Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1  RGMII/RMII/MII Timing Conditions
        2. 7.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 7.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 7.12.3.4  RGMII Receive Clock Timing Requirements
        5. 7.12.3.5  RGMII RX and TX Timing Diagrams
        6. 7.12.3.6  RGMII Receive Data and Control Timing Requirements
        7. 7.12.3.7  RMII Transmit Clock Switching Characteristics
        8. 7.12.3.8  RMII Transmit Data and Control Switching Characteristics
        9. 7.12.3.9  RMII Receive Clock Timing Requirements
        10. 7.12.3.10 RMII Receive Data and Control Timing Requirements
        11. 7.12.3.11 MII Transmit Switching Characteristics
        12. 7.12.3.12 MII Receive Clock Timing Requirements
        13. 7.12.3.13 MII Receive Timing Requirements
        14. 7.12.3.14 MII Transmit Clock Timing Requirements
        15. 7.12.3.15 MDIO Interface Timings
      4. 7.12.4 LVDS Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5 UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements#GUID-5F6D5D17-1161-44B3-ABD1-283215937B93/T4362547-185
      7. 7.12.7 Enhanced Pulse-Width Modulator (ePWM)
      8. 7.12.8 General-Purpose Input/Output
        1. 7.12.8.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)#GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-45#GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short and Medium Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

4 Device Comparison

Table 4-1 Device Features Comparison
FUNCTION AWR2544 AWR2944 AWR2243 AWR1843
Launch on Package (LOP) Antenna Yes

—

 — —
Number of receivers 4 4 4 4
Number of transmitters 4 4 3(1) 3(1)
On-chip memory 2MB 4MB — 2MB
Max I/F (Intermediate Frequency) (MHz) 20 15 (2) 20 10
Max real/complex 2x sampling rate (Msps) 45(2)

37.5

 45 25
Max complex 1x sampling rate (Msps) —(2)

—

 22.5 12.5
Safety and Security(3)
Hardware Security Module (HSM) (6)

Yes

Yes

 — —
Security Accelerators (6)

Yes

Yes

 —

Yes
AEC-Q100 Qualified Yes

Yes

 Yes Yes
Processor
DSP (C6xx)

—

Yes

—

 Yes
MCU (RxF) Yes(4) Yes(5) — Yes
Hardware accelerator Yes(5) Yes(6) — Yes
Peripherals
Serial Peripheral Interface (SPI) ports 1 2 1 2
Quad Serial Peripheral Interface (QSPI)

1

 Yes — Yes
LVDS/Debug Yes Yes Yes Yes
Aurora LVDS — Yes — —
Ethernet Interface Yes Yes — —
Inter-Integrated Circuit (I2C) interface 1 1 1 1
Controller Area Network (DCAN) interface — — — Yes
CAN FD — 2 — 1
Trace Yes Yes — Yes
EPWM Yes Yes — Yes
DMM Interface — Yes — Yes
GPADC Yes Yes(7) Yes Yes
CSI2 TX Yes — Yes —
CSI2 RX — Yes — —
Cascade (20-GHz sync) — — Yes —
JTAG Yes Yes — Yes
Per chirp configurable Tx phase shifter Yes Yes Yes Yes
Product status(7) PRODUCT PREVIEW (PP),
ADVANCE INFORMATION (AI),
or PRODUCTION DATA (PD)		 AI PD PD PD
(1) 3 Tx Simultaneous operation in AWR1843 and AWR2243 is supported only with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin. Please refer to the respective datasheets for more information.
(2) AWR2544 supports a real only receiver.
(3) Developed for Functional Safety applications, the AWR2544 device is targeted to support hardware integrity up to ASIL-B. For other devices, refer to the respective Datasheets.
(4) In AWR2544, Main-Subsytem Processing core is changed from ARM CR4F in AWR1843 to ARM CR5F.
(5) The hardware accelerator in AWR2544 is upgraded to HWA1.5 with additional features as compared to AWR1843.
(6) Only applicable for AWR2544 Secure Part Variant
(7) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of allparameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.