SWRS325A December   2024  – December 2025 AWRL6844

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
      13.      23
      14.      24
      15.      25
      16.      26
      17.      27
      18.      28
    3.     29
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 3.3V I/O Topology
      2. 7.6.2 1.8V I/O Topology
      3. 7.6.3 System Topologies
        1. 7.6.3.1 I/O Topologies
      4. 7.6.4 RF Supply Decoupling Capacitor and Layout Conditions
        1. 7.6.4.1 1.2V RF Supply Rail
          1. 7.6.4.1.1 1.2V RF Rail
        2. 7.6.4.2 1.0V RF LDO
          1. 7.6.4.2.1 1.0V RF LDO
      5. 7.6.5 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  RF Specification
    10. 7.10 Supported DFE Features
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Timing and Switching Characteristics
      1. 7.13.1  Power Supply Sequencing and Reset Timing
      2. 7.13.2  Synchronized Frame Triggering
      3. 7.13.3  Input Clocks and Oscillators
        1. 7.13.3.1 Clock Specifications
      4. 7.13.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.13.4.1 McSPI Features
        2. 7.13.4.2 SPI Timing Conditions
        3. 7.13.4.3 SPI—Controller Mode
          1. 7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.13.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.13.4.4 SPI—Peripheral Mode
          1. 7.13.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.13.5  LVDS Instrumentation and Measurement Peripheral
        1. 7.13.5.1 LVDS Interface Configuration
        2. 7.13.5.2 LVDS Interface Timings
      6. 7.13.6  LIN
      7. 7.13.7  General-Purpose Input/Output
        1. 7.13.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.13.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.13.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 7.13.9  Serial Communication Interface (SCI)
        1. 7.13.9.1 SCI Timing Requirements
      10. 7.13.10 Inter-Integrated Circuit Interface (I2C)
        1. 7.13.10.1 I2C Timing Requirements
      11. 7.13.11 Quad Serial Peripheral Interface (QSPI)
        1. 7.13.11.1 QSPI Timing Conditions
        2. 7.13.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.13.11.3 QSPI Switching Characteristics
      12. 7.13.12 JTAG Interface
        1. 7.13.12.1 JTAG Timing Conditions
        2. 7.13.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.13.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1  RF and Analog Subsystem
      2. 8.3.2  Clock Subsystem
      3. 8.3.3  Transmit Subsystem
      4. 8.3.4  Receive Subsystem
      5. 8.3.5  Processor Subsystem
      6. 8.3.6  Automotive Interface
      7. 8.3.7  Host Interface
      8. 8.3.8  Application Subsystem Cortex-R5F
      9. 8.3.9  DSP Subsystem
      10. 8.3.10 Hardware Accelerator (HWA1.2) Features
        1. 8.3.10.1 Hardware Accelerator Feature Differences Between HWA1.1 in xWRx843, HWA1.2 in xWRLx432 and HWA1.2 in xWRL684x
    4. 8.4 Other Subsystems
      1. 8.4.1 Security – Hardware Security Module
      2. 8.4.2 GPADC Channels (Service) for User Application
      3. 8.4.3 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

12 Revision History

Changes from January 1, 2025 to December 31, 2026 (from Revision * (January 2025) to Revision A (December 2025))

  • (Features) : Updated typical output power per TX to 12.5dBmGo
  • (Features) : Updated typical phase noise at 1MHz offset to -90.5dBc/HzGo
  • (Features) : Added LIN interface under host interfacesGo
  • (Features) : Added product cybersecurity compliance informationGo
  • (Packaging Information) : Pre-production part numbers removedGo
  • (Functional Block Diagram) : Added crypto accelerators and Secure zoneGo
  • (Functional Block Diagram) : Added Always on DomainGo
  • (Functional Block Diagram figure notes) : Added available transmitter antenna info for AWRL6843 Go
  • (Device Comparison) : Production status changed from AI to PDGo
  • (Device Comparison) : Added HWA versionsGo
  • (Device Comparison) : Added cybersecurity complianceGo
  • (Signal Descriptions) : Added DSS UARTA signal description Go
  • (Analog Signal Descriptions) : Added available transmitter antenna info for AWRL6843 Go
  • (Valid IOSET Combinations for SPIB Signal) : Updated additional SPIB IOSET combinationsGo
  • (System Signal Descriptions) : Updated System Signal DescriptionsGo
  • (System Signal Descriptions) : Updated BGA pins available for PRCM_PMIC_Deepsleep and WU_reqinGo
  • (Recommended Operating Conditions for OTP eFuse Programming) : Added decoupling capacitor recommendationGo
  • (RF Supply Decoupling Capacitor and Layout Conditions) : Updated parasitics requirements for 1.2V RF rail and 1.0V RF LDO outputGo
  • (RF Supply Decoupling Capacitor and Layout Conditions) : Added min-max capacitor requirements for 1.2V RF rail and 1.0V RF LDO outputGo
  • (RF Supply Decoupling Capacitor and Layout Conditions) : Added layout guidellines for for 1.2V RF rail and 1.0V RF LDO outputGo
  • (Typical Power Consumption Numbers) : Introduction updated with the status of I/Os Go
  • (Typical Power Consumption Numbers) : Estimated Power Consumed in 3.3V IO Mode table - updated power consumption numbers.Go
  • (Typical Power Consumption Numbers) : Estimated Power Consumed in 3.3V IO Mode table - updated configuration with more details.Go
  • (Typical Power Consumption Numbers) : Estimated Power Consumed in 1.8V IO Mode table added.Go
  • (Typical Power Consumption Numbers) : Use-Case Power Consumed in 3.3V I/O Topology - updated power consumption numbers.Go
  • (Typical Power Consumption Numbers) : Use-Case Power Consumed in 3.3V I/O Topology - updated configuration with more details.Go
  • (Typical Power Consumption Numbers) : Use-Case Power Consumed in 1.8V IO Mode table added.Go
  • (Peak Current Requirement per Voltage Rail) : Maximum Peak Current per Voltage Rail table - updated peak current numbersGo
  • (RF Specification) : Updated typical TX output power to 12.5dBmGo
  • (RF Specification) : Updated typical phase noise at 1MHz offset to -90.5dBc/HzGo
  • (RF Specification) : Updated receiver S11 to -7dBGo
  • (RF Specification) : Updated transmitter S11 to -7.5dBGo
  • (RF Specification) : Added a plot of Noise Figure, In-band P1dB vs Receiver GainGo
  • (Supported DFE Features) : Updated RX gain range to 36dB to 46dBGo
  • (Supported DFE Features) : Chip Profile Supported by Timing Engine figure - Updated typical inter-chirp idle time to 6 to 12uSGo
  • (Supported DFE Features) : Chip Profile Supported by Timing Engine figure - Updated typical inter-burst idle time to 135 to 270uSGo
  • (Power Supply Sequencing and Reset Timing) : Updated Device Wake-up Sequence diagram to sequence 1.2V rail before 1.8V rail.Go
  • (Functional Block Diagram) : Added crypto accelerators and Secure zoneGo
  • (Functional Block Diagram) : Added Always on DomainGo
  • (Functional Block Diagram figure notes) : Added available transmitter antenna info for AWRL6843 Go
  • (GPADC Channels (Service) for User Application) : Updated the introduction related to GPADC readings to the reflect actual GPADC measurement info.Go
  • (Memory Partitioning Options) : Updated DSS L3 total memory to 896KB in default option and 0KB to alternative option for AWRL6843.Go