SWRS326A December   2024  – December 2025 IWRL6844

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
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      6.      16
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      8.      18
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      11.      21
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    3.     28
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 3.3V I/O Topology
      2. 7.6.2 1.8V I/O Topology
      3. 7.6.3 System Topologies
        1. 7.6.3.1 I/O Topologies
      4. 7.6.4 RF Supply Decoupling Capacitor and Layout Conditions
        1. 7.6.4.1 1.2V RF Supply Rail
          1. 7.6.4.1.1 1.2V RF Rail
        2. 7.6.4.2 1.0V RF LDO
          1. 7.6.4.2.1 1.0V RF LDO
      5. 7.6.5 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  RF Specification
    10. 7.10 Supported DFE Features
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Timing and Switching Characteristics
      1. 7.13.1  Power Supply Sequencing and Reset Timing
      2. 7.13.2  Synchronized Frame Triggering
      3. 7.13.3  Input Clocks and Oscillators
        1. 7.13.3.1 Clock Specifications
      4. 7.13.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.13.4.1 McSPI Features
        2. 7.13.4.2 SPI Timing Conditions
        3. 7.13.4.3 SPI—Controller Mode
          1. 7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.13.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.13.4.4 SPI—Peripheral Mode
          1. 7.13.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.13.5  LVDS Instrumentation and Measurement Peripheral
        1. 7.13.5.1 LVDS Interface Configuration
        2. 7.13.5.2 LVDS Interface Timings
      6. 7.13.6  General-Purpose Input/Output
        1. 7.13.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 7.13.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.13.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.13.8  Serial Communication Interface (SCI)
        1. 7.13.8.1 SCI Timing Requirements
      9. 7.13.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.13.9.1 I2C Timing Requirements
      10. 7.13.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.13.10.1 QSPI Timing Conditions
        2. 7.13.10.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.13.10.3 QSPI Switching Characteristics
      11. 7.13.11 JTAG Interface
        1. 7.13.11.1 JTAG Timing Conditions
        2. 7.13.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.13.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Host Interface
      7. 8.3.7 Application Subsystem Cortex-R5F
      8. 8.3.8 DSP Subsystem
      9. 8.3.9 Hardware Accelerator (HWA1.2) Features
        1. 8.3.9.1 Hardware Accelerator Feature Differences Between HWA1.1 in xWRx843, HWA1.2 in xWRLx432 and HWA1.2 in xWRL684x
    4. 8.4 Other Subsystems
      1. 8.4.1 Security – Hardware Security Module
      2. 8.4.2 GPADC Channels (Service) for User Application
      3. 8.4.3 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

1 Features

  • FMCW Transceiver
    • Integrated PLL, transmitter, receiver, baseband and ADC
    • 57 - 64GHz coverage with 7GHz continuous bandwidth
    • 4 receive channels and 3 to 4 transmit channels (IWRL6843 with 3 channels and IWRL6844 with 4 channels)
    • 12.5dBm typical output power per TX
    • 12.5dB typical noise figure
    • -90.5dBc/Hz typical phase noise at 1MHz
    • FMCW operation
    • 10MHz IF bandwidth, real-only Rx channels
    • Ultra-accurate chirp engine based on fractional-N PLL
    • Per transmitter binary phase shifter
  • Processing elements
    • Arm®R5F® core with double precision FPU (200MHz)
    • Hardware Accelerator (HWA 1.2) for FFT, log magnitude, and CFAR operations (200MHz)
    • C66x DSP (450MHz) for processing Radar data
  • Supports multiple low-power modes
    • Idle mode and deep sleep mode
  • Power management
    • 1.8V and 3.3V IO support
    • Built-in LDO network for enhanced PSRR
    • Two power rails for 1.8V IO mode, Three power rails for 3.3V IO mode
  • FCCSP package having 17 x 17 BGA grid, 207 BGA balls; Package size: 9.1mm x 9.1mm
  • Built-in calibration and self-test
    • Built-in Firmware (ROM)
    • Self-Contained on chip calibration system
  • Host Interfaces
    • 3 x UART
    • 2 x CAN-FD
    • 2 x SPI
  • LVDS for data transfer of raw ADC sample capture
  • Other interfaces available to user application
    • QSPI
    • I2C
    • JTAG
    • 8 x GPIOs
    • PWM Interface
    • 4 x GPADCs
  • Device security (on Secure device variants)
    • Programmable embedded hardware security module (HSM)
    • Secure authenticated and encrypted boot support
    • Customer programmable root keys, symmetric keys (256 bit), asymmetric keys (up to RSA-4K or ECC-512) with key revocation capability
    • Cryptographic hardware accelerators: PKA with ECC/RSA, AES (up to 256 bit), SHA (up to 512 bit), TRNG/DRBG and SM2, SM3, SM4(Chinese Crypto Algorithms)
    • Product Cybersecurity Compliance
      • Developed for cybersecurity-relevant applications
      • Documentation will be available to aid cybersecurity system design
  • Internal memory

    • On-Chip RAM - 2.5MBytes (2MBytes for IWRL6843) including

      • R5F TCMA RAM - 512KB
      • R5F TCMB RAM - 256KB
      • DSS L2 RAM - 384KB
      • DSS L3 RAM - 512KB (available only in IWRL6844)
      • DSS L3 Shared RAM - 896KB (can be shared with TCMs)
  • Functional Safety-Compliant Targeted
    • Developed for Functional Safety Applications
    • Documentation will be available to aid functional safety system design
    • Hardware integrity up to SIL 2 targeted as per IEC61508 standard
  • Clock source
    • 40.0MHz crystal for primary clock
    • Supports externally driven clock (Square/Sine) at 40.0MHz
    • 32kHz internal oscillator for low power operations
  • Operating temperature range
    • Junction Temperature Range: –40°C to 105°C