SWRZ137C December   2022  – December 2025 IWRL6432

PRODUCTION DATA  

  1.   1
  2.   ABSTRACT
  3. 1Introduction
  4. 2Device Nomenclature
  5. 3Device Markings
  6. 4Usage Notes
    1. 4.1 Power up sequence in power optimized topology
    2. 4.2 Meeting data sheet spec for 1.2V Digital LDO output path in BOM optimized topology
  7. 5Advisory to Silicon Variant / Revision Map
  8. 6Known Design Exceptions to Functional Specifications
    1. 6.1  ANA #48
    2. 6.2  ANA #49
    3. 6.3  ANA #50
    4. 6.4  ANA #51
    5. 6.5  ANA #52
    6. 6.6  ANA #57
    7. 6.7  DIG #1
    8. 6.8  DIG #2
    9. 6.9  DIG #3
    10. 6.10 DIG #4
    11. 6.11 DIG #5
    12. 6.12 DIG #6
    13. 6.13 DIG #7
    14. 6.14 DIG #8
    15. 6.15 DIG #9
    16. 6.16 DIG #10
    17. 6.17 DIG #14
    18. 6.18 DIG #15
    19. 6.19 DIG #16
  9. 7Trademarks
  10.   Revision History

5 Advisory to Silicon Variant / Revision Map

Table 5-1 Advisory to Silicon Variant / Revision Map
Advisory Number Advisory Title IWRL6432 IWRL6432
ES1.0 ES2.0
Analog / Millimeter Wave

ANA #48

 Reduction in supported RF frequency range x

ANA #49

 Analog temperature sensor: Not usable at high temperatures x

ANA #50

GPADC based external signal monitor is not supported

 x
ANA #51

Continuous Wave Streaming CZ mode: Sudden jump in RX output codes every 20.97152msec

 x x
ANA #52 Slicer LDO Test LOAD (TLOAD) not disabled after startup x
ANA #57 SNR degradation at 60GHz in the presence of strong near range reflector x x
Digital Subsystem
DIG #1 ePWM: Glitch during Chopper mode of operation x x
DIG #2 UART A cannot be used to wake up the sequencer from Deep Sleep Low Power Mode x
DIG #3 Limited UART baud rates x x
DIG #4 RS232 AutoBaud Rate feature doesn't support trimmed ROCSC variation. x x
DIG #5 Internal Bus access to SPI for data transfer not supported when SPI smart-idle mode is enabled. x x
DIG #6 CRC: CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supported x x
DIG #7 APPSS Cortex-M4 doesn't get the correct error response when cluster 3 retention memories are accessed in low-power deep-sleep powered down state x
DIG #8 Shared RAM clock gating default values x x
DIG #9 TOP_IO_MUX register space not accessible from RS232 for debug purposes. x x
DIG #10 Incorrect behavior of frame stop API x x
DIG #14 Corrupted Data Store for Partial Write in Shared Memory x x
DIG #15 Boot failure, if metaimage is multiple of 2K x
DIG #16 Boot failure for images less than size 8k over SPI x x