TIDT367 December   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Required Equipment
    3. 1.3 Test Setup
      1. 1.3.1 Hardware Setup
      2. 1.3.2 Software Setup
    4. 1.4 Running the Code for Different Labs
      1. 1.4.1 Lab 1. Primary to Secondary Power Flow, Open Loop Check PWM Driver
      2. 1.4.2 Lab 2. Primary to Secondary Power Flow, Open Loop CheckPWM Driver and ADC With Protection
      3. 1.4.3 Lab 3. Primary to Secondary Power Flow, Closed Voltage Loop Check
      4. 1.4.4 Lab 4. Primary to Secondary Power Flow, Closed Current Loop Check
      5. 1.4.5 Lab 6. Secondary to Primary Power Flow, Open Loop Check PWM Driver
      6. 1.4.6 Lab 7. Secondary to Primary Power Flow, Open Loop Check PWM Driver and ADC With Protection
      7. 1.4.7 Lab 8. Secondary to Primary Power Flow, Closed Voltage Loop Check
  6. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Efficiency Data
    3. 2.3 Thermal Images
    4. 2.4 Bode Plots
  7. 3Waveforms
    1. 3.1 Switching
    2. 3.2 Load Transients
    3. 3.3 Start-Up Sequence
    4. 3.4 Dynamic Response
    5. 3.5 Mode Transition

1.4.6 Lab 7. Secondary to Primary Power Flow, Open Loop Check PWM Driver and ADC With Protection

In this build, the board is excited in open-loop fashion with a specified frequency that can be changed through the watch window. The frequency is controlled with the CLLLC_pwmPeriodRef_pu variable. The power flow is from the secondary side to the primary side. Set the load current above 1 A to avoid the unregulated output voltage in open loop.

  1. Run the project by clicking the Resume button in the Tool Bar
  2. Set the load current below 2 A during start up
  3. Clear the trip by writing “1” to the CLLLC_clearTrip variable in the watch window
  4. Now, slowly increase the input VSEC DC voltage from 0 V to 48 V. Make sure CLLLC_vSecSensed_Volts displays the correct values in the watch window
  5. The VPRIM variable shows a voltage of close to 400 V per the tank gain designed. Verify that CLLLC_vPrimSensed_Volts shows the correct voltage.
  6. Test to see operation under different frequencies (that is, above resonance, below resonance)