TIDUE73A April   2018  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000 Real-Time MCU LaunchPad
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.5.2 FRAME_STATE Generation

This section discusses in depth the FRAME_STATE generation. The FRAME_STATE is responsible for determining which of clocks are generated at any given time within the transaction.

The FRAME_STATE (FSM_1 s1, s0) transitions through 4 states:

  • IDLE:
    • No activity
    • The CLB waits for the rising edge of the START_OPERATION signal to begin transmitting the encoder clock.
  • TRANSMIT_MA:
    • Transmit the encoder clock
    • Monitor the response for the ACK from the encoder
  • TRANSMIT_MA_AND_RECEIVE_SL
    • Continue to transmit the encoder clock
    • Start the SPI clock to receive the response
    • During this time both the encoder clock and the SPI clock are active.
  • RECEIVE_SL:
    • The transmission of encoder clock is complete
    • The CDM bit is active on the MA signal
    • Finish receiving the response by clocking the SPI.
    • Depending on the length of the data and the SPI width used, additional SPI clocks can be generated to trigger a SPI interrupt.
TIDM-1010 FRAME_STATE Generation Figure 2-13 FRAME_STATE Generation

One method to derive the corresponding equations is to use a Karnaugh map (Table 2-5, and Table 2-6). The resulting equations are combined by an OR operator and entered into the CLB tool. The equations do not need to be reduced to the simplest form.

Table 2-5 FRAME_STATE FSM_1 Karnaugh Map, State s0
Current Input
(e1, e0)
RESPONSE_RE, START_OPERATION or ENCODER_CLOCK_COMPLETE
0,0 0,1 1,1 (1) 1,0
Previous State
s1, s0		 0,0
IDLE		 0 1 (2) 1 (2) 0
0,1
TRANSMIT_MA		 1 (3) 1 (3) 0 0
1,1
RECEIVE_SL		 1 (4) 1 (4) 1 (4) 1 (4)
1,0
TRANSMIT_MA
RECEIVE_SL		 0 1 (5) 1 (5) 0
(1) Corresponds to an invalid, or unexpected, e1:e0 combination. The system designer decides the behavior of the state machine in such cases.
(2) !s1 & !s0 & e0
(3) !s1 & s0 & !e1
(4) s1 & s0. The C28x forces the transition from state 1,1 back to IDLE.
(5) s1 & !s0 & e0
Table 2-6 FRAME_STATE FSM_1 Karnaugh Map, State s1
Current Input
(e1, e0)
RESPONSE_RE, START_OPERATION or ENCODER_CLOCK_COMPLETE
0,0 0,1 1,1 1,0
Previous State
s1, s0		 0,0
IDLE		 0 0 0 0
0,1
TRANSMIT_MA		 0 0 1 (1) 1 (1)
1,1
RECEIVE_SL		 1 (2) 1 (2) 1 (2) 1 (2)
1,0
TRANSMIT_MA RECEIVE_SL		 1 (3) 1 (3) 1 (3) 1 (3)
(1) !s1 & s0 & e1
(2) s1 & s0. The C28x forces the transition from state 1,1 back to IDLE.
(3) s1 & !s0

The OUT signal from FSM_1 corresponds to the IDLE state.

Detection of the encoder's response is another key component of the design. LUT_2, shown in Figure 2-13, is responsible for detecting the encoder's ACK. If the FRAME_STATE is WAIT_FOR_ACK (0,1) and ENCODER_RESPONSE_RE goes high, then ACK has been detected. This results in the equation: i0 & (i1 & !i2):

  • i0 == 1: ENCODER_RESPONSE_RE goes high
  • (!i2 & i1) == FRAME_STATE == WAIT_FOR_ACK (0,1)