TIDUEV4B December   2019  – November 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1  Processor – i.MX 7Dual Applications Processor
      2. 2.2.2  i.MX 7Dual Memory Interfaces
        1. 2.2.2.1 DDR3L
        2. 2.2.2.2 Quad SPI NOR Flash
        3. 2.2.2.3 eMMC iNAND
        4. 2.2.2.4 SD Card Connector
      3. 2.2.3  Audio CODEC
      4. 2.2.4  USB to UART Converter
      5. 2.2.5  USB Ports
      6. 2.2.6  LCD Screen Connector
      7. 2.2.7  Mobile Industry Processor Interface (MIPI) CSI Connector
      8. 2.2.8  Mini PCI Express Connector
      9. 2.2.9  CAN Transceiver and Standard Connector
      10. 2.2.10 JTAG Header
      11. 2.2.11 USB2ANY Header
      12. 2.2.12 Functional Switches and Status LEDs
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS6521815 - Power Management IC
      2. 2.3.2 WL1831MOD - Wi-Fi + Bluetooth Module
      3. 2.3.3 DP83867CR - Ethernet PHY
      4. 2.3.4 OPT3001 - Ambient Light Sensor
      5. 2.3.5 INA3221 - Current Monitor
      6. 2.3.6 TPS3808 - Voltage Supervisor for Reset Scheme
      7. 2.3.7 TLV755P, TPS62067, TPS51200 - Auxiliary Power
    4. 2.4 System Design Theory
      1. 2.4.1 Power Estimation
      2. 2.4.2 Power Sequencing
      3. 2.4.3 I2C Device Chain
      4. 2.4.4 Clock Scheme
      5. 2.4.5 BOOT Configuration
      6. 2.4.6 PCB Floor Planning
  9. 3Getting Started, Testing Setup, and Test Results
    1. 3.1 Getting Started With Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Onboard LED Information
      2. 3.1.2 Software
        1. 3.1.2.1 Booting of TIDA-050034
        2. 3.1.2.2 Example Linux Commands for Testing TIDA-050034
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 CAD Files
    4. 4.4 Gerber Files
    5. 4.5 Assembly Drawings
  11. 5Software Files
  12. 6Documentation Support
    1. 6.1 Trademarks
    2.     59
  13. 7Revision History
  14.   A Processor Pin Mapping
    1.     A.1 i.MX 7Dual Pin Mapping

2.4.5 BOOT Configuration

This design uses two BOOT configuration. BOOT Mode pins controlled by SW3 DIP switches are connected to dedicated BOOT_MODE0 and BOOT_MODE1 input pins of i.MX 7D Processor. Along with these, there are 20 different pins for setting Booting configuration which shares pins with LCD Data. These 20 pins are controlled by the 8 DIP Switches of SW2. All of the possible BOOT options are given in Table 2-4 (SW3) and Table 2-5 (SW2).

Table 2-4 SW3 BOOT Mode Settings
BOOT_MODE[1..0]BIT 1BIT 0
Fuses00
Serial Download01
Internal BOOT10
Test Mode11
Table 2-5 SW2 BOOT Mode Settings
SW2, pin 1SW2, pin 2SW2, pin 3SW2, pin 4SW2, pin 5SW2, pin 6SW2, pin 7SW2, pin 8
BT_CFG[14]BT_CFG[13]BT_CFG[12]BT_CFG[11]BT_CFG[10]BT_CFG[6]BT_CFG[5]BT_CFG[4]
001b = SD/eSD BootPort Select:
00b=eSDHC1,
01b=eSDHC2,
10b=eSDHC3		0b0bBus Width: 0b=1-bit, 1b=4-bit
010b = MMC/eMMC BootBus Width:
000b=1-bit, 001b=4-bit, 010b=8-bit,
101b=4-bit DDR (MMC4.4),
110b=8-bit DDR (MMC4.4)
011b = NAND BootPages In Block:
00b=128, 01b=64, 10b=32, 11b=256		BOOT_SEARCH_COUNT:
00b=2, 01b=2, 10b=4, 11b=8		0b
100b = QSPI Boot0b0b0b0b0b