TIDUF34 july   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1  DP83TD510E
      2. 2.3.2  AM2434
      3. 2.3.3  TPS2660
      4. 2.3.4  TPS79801-Q1
      5. 2.3.5  MSP430FR2476
      6. 2.3.6  TLV7031
      7. 2.3.7  ATL431
      8. 2.3.8  LM74700-Q1
      9. 2.3.9  TPS62825A
      10. 2.3.10 TPS61023
      11. 2.3.11 TLVM13630
      12. 2.3.12 LSF0108
  9. 3System Design Theory
    1. 3.1 Power Supply
    2. 3.2 PoDL PD and Coupling Network
    3. 3.3 Sitara Technology Module
    4. 3.4 Boot Mode
    5. 3.5 PHI and BoosterPack Headers
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Boot Switch Configuration
      2. 4.1.2 Reference Design Start-Up
    2. 4.2 Software Requirements
      1. 4.2.1 PD Firmware
      2. 4.2.2 MCU Firmware
    3. 4.3 Test Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

PoDL PD and Coupling Network

For implementation of PoDL, the data and power path must get separated. The power path is handled by the powered device (PD), the data path can be fed directly to the Ethernet PHY.

Figure 3-6 shows a simplified image of the implementation of this coupling network. PoDL is accomplished with a small transformer instead of capacitive coupling, not because of the higher isolation voltage, but specifically because the small transformer is more robust to common-mode noise. To use a transformer with power, a split winding on the cable side is beneficial, so a capacitor for DC blocking can be inserted. Also, an AC common-mode termination can be inserted at this point on the cable side.


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Figure 3-6 PoDL Implementation

The common-mode choke is on the cable side of this circuit, so the choke also blocks noise coming from the power supply; therefore, the common-mode choke must be rated for this current.

For the low-frequency path going to the PD, a differential-mode choke is used, the inductance has a direct influence on the droop of the signal coming from the Ethernet PHY. The higher the inductance, the lower the droop. However, a large inductance is bigger and more expensive. So the selection is always a trade-off between these parameters. Using two separate inductors here is possible, but this also increases the space requirements. To provide the possibility to evaluate different implementations, the PCB features multiple footprints for all magnetic parts.

The PD is programmed to make use of the serial communication classification protocol (SCCP) to communicate to a power sourcing equipment (PSE) being a type E and power class 12 device. More details about the implementation of a powered device (PD) are found in the IEEE 802.3cg 10BASE-T1L Power over Data Lines Powered Device Design application note.