TIDUF86A January   2025  – July 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 System Overview
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG3100
      2. 2.3.2 LMR38010
      3. 2.3.3 TMP61
      4. 2.3.4 TPS7B81
      5. 2.3.5 OPA4323
  9. 3System Design Theory
    1. 3.1 Power Stage Design: Three-Phase Inverter
    2. 3.2 LMG3100 GaN-FET Power Stage
    3. 3.3 Power Management
    4. 3.4 Current-Sensing Circuit
    5. 3.5 Overcurrent Protection Circuit
    6. 3.6 Phase Voltage and DC Input Voltage Sensing
    7. 3.7 Power-Stage PCB Temperature Monitor
    8. 3.8 Interface to Host MCU
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 TIDA-010276 PCB Overview
      2. 4.1.2 TIDA-010276 Jumper Settings
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Power Management and System Power Up and Power Down
      2. 4.3.2 GaN Inverter Switch Node Voltage
      3. 4.3.3 Switch Node Voltage Transient Response
      4. 4.3.4 Impact of PWM Frequency to DC-Bus Voltage Ripple
      5. 4.3.5 Efficiency Measurements
      6. 4.3.6 Thermal Analysis
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

3.2 LMG3100 GaN-FET Power Stage

The LMG3100 incorporates a high-side level shifter and bootstrap circuit, so that two LMG3100 devices can be used to form a half bridge without needing an additional level shifter. The PCB space is further reduced due to high integration and the fact that only a few additional passive components are required. Figure 3-2 shows the schematic of one half-bridge.


TIDA-010276 TIDA-010276 GaN Power Stage Schematic for Phase U

Figure 3-2 TIDA-010276 GaN Power Stage Schematic for Phase U

The 36V DC-link voltage is connected to the LMG3100 VIN pin and referenced to the power ground (PGND) pin. Local ceramic bypass capacitors C51, C52, C53, C54, and C55 (1μF) and C69, C70, C71, C72, and C66 (220nF) are placed in parallel, close between the VIN and AGND pins to minimize loop inductance. Capacitor C85 is also added in half-bridge DRN and SRC to reduce the switch noise.

The LMG3100 integrated gate driver is supplied with 5V. A 1μF and 0.1μF ceramic bypass capacitor (C130, C86) are placed close to the VCC pin and AGND pin in the low-side GaN FET, as suggested in the data sheet. A 100nF ceramic bootstrap capacitor (C95) is placed close to the high-side gate-driver bootstrap rail and high-side GaN-FET source connection pins. R6 and R12 in the VCC path can limit the turn-on slew rate of the GaN FET. A 3Ω resistor was used for the tests in this design for R5 and R7. The complementary PWM signals for the high-side and low-side switch from the PWM buffer are low-pass filtered with R15, C89 and R18, C92 to reject high-frequency impulse noise and avoid false switching with a cutoff frequency of around 160MHz and a propagation of around 1ns. Since this is a half-bridge application, connect the AGND of the high-side GaN FET to the low-side DRN pin. Because the low-side current sampling is used, connect AGND to the upper end of the sampling resistor and make sure that the voltage drop on the sampling resistor is as small as possible.

For layout, capacitors C55 to C69 need to be connected to the AGND network and make the connections as short as possible. Connect C85 as close as possible to the Phase_U network.