The TPS2HCS10-Q1 can automatically wake up the MCU when load current increases on either device output during LPM. This load wake-up event connects the nFLT pin of the TPS2HCS10-Q1 to a logic circuit built into a TPLD1201-Q1. When load current increases, the nFLT pin goes low which triggers the TPLD circuit to pull the PMIC wake high. During system wakeup, the TPS2HCS10-Q1 automatically transitions from delivering current to the load from the bypass path to the active path, which supports full load operation.

The TPS2HCS10-Q1 requires additional logic within the TPLD1201-Q1 to wake up the MCU when compared to other load drivers. When the TPS2HCS10-Q1 sees load current increase at either output, the nFLT pin goes low for 100μs, thus the TPLD1201-Q1 output remains high for 100μs as well. However, the PMIC requires a minimum 2ms pulse on the WAKE pin to wake up due to the configured glitch time. To overcome this challenge, additional logic within the TPLD1201-Q1 is added to capture the transition of the TPS2HCS10-Q1 nFLT pin on the falling edge from high to low by latching this value for 3ms.

By latching the TPLD1201-Q1 wake output high for well above the PMIC required pulse time, the system can now wake up with TPS2HCS10-Q1. Figure 3-13 shows the nFLT pin of the TPS2HCS10-Q1 transitioning high to low when the device sees an increase in output current, and the TPLD holds the output high for a time of 3ms to trigger the PMIC WAKE.

Figure 3-13 TPS2HCS10-Q1 Automatic Load Wakeup