TIDUFB5A December   2024  – January 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Redundant Input Supplies
      2. 2.2.2 Ethernet Ring
      3. 2.2.3 Audio Video Bridging (AVB)
      4. 2.2.4 Low-Power Mode and Wake
      5. 2.2.5 Limp Home Mode
      6. 2.2.6 SPI Daisy Chain
      7. 2.2.7 Reset Aggregation
    3. 2.3 Highlighted Products
      1. 2.3.1  AM263P4-Q1
      2. 2.3.2  DP83TG721S-Q1
      3. 2.3.3  DP83TD555J-Q1
      4. 2.3.4  TPS653860-Q1
      5. 2.3.5  TPS2HCS10-Q1
      6. 2.3.6  TPS2HCS05-Q1
      7. 2.3.7  DRV8245S-Q1
      8. 2.3.8  TIC12400-Q1
      9. 2.3.9  LM74900-Q1
      10. 2.3.10 LM74703-Q1
      11. 2.3.11 INA186-Q1
      12. 2.3.12 TPS7B81-Q1
      13. 2.3.13 TPS3762-Q1
      14. 2.3.14 TPS62903-Q1
      15. 2.3.15 TPS62902-Q1
      16. 2.3.16 TPS7B4256-Q1
      17. 2.3.17 TPS1211-Q1
      18. 2.3.18 TPS1HC30-Q1
      19. 2.3.19 TPS4HC120-Q1
      20. 2.3.20 TPS2HC08-Q1
      21. 2.3.21 TPS1HC04-Q1
      22. 2.3.22 DRV8714S-Q1
      23. 2.3.23 DRV8145S-Q1
      24. 2.3.24 DRV81602-Q1
      25. 2.3.25 TPS1214-Q1
      26. 2.3.26 TCAN1043A-Q1
      27. 2.3.27 TCAN1044-Q1
      28. 2.3.28 TCAN1046V-Q1
      29. 2.3.29 SN3257-Q1
      30. 2.3.30 TLIN1021A-Q1
      31. 2.3.31 TLIN1024A-Q1
      32. 2.3.32 TAS6754-Q1
      33. 2.3.33 TMUX1308-Q1
      34. 2.3.34 TPLD1201-Q1
      35. 2.3.35 SN74CBTLV3861-Q1
      36. 2.3.36 TXE8124-Q1
      37. 2.3.37 TCAL9539-Q1
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
      1. 3.4.1 Redundant Input Supply
      2. 3.4.2 Power Sequence
      3. 3.4.3 Reset Aggregation
      4. 3.4.4 Low Power Mode Tests
        1. 3.4.4.1 Low Power Mode Quiescent Current
        2. 3.4.4.2 Wake Measurement Results
        3. 3.4.4.3 CAN Wake
        4. 3.4.4.4 LIN Wake
        5. 3.4.4.5 High-Side Switch Controller Wake
        6. 3.4.4.6 Smart eFuse Wake
        7. 3.4.4.7 High-Side Switch Wake
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 Layout
      3. 4.1.3 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

Features

  • MCU with integrated Ethernet switch to optimize Ethernet ring topologies by implementing the following hardware protocols:
    • 802.1Qav, 802.1Qbv, 802.1cb (partial),
      1588 TE, and 802.1Q ALE
  • AVB Ethernet audio support with Ethernet PHY hardware time stamping and integrated media clock adjustment
  • ASIL D-rated MCU and PMIC with system Limp Home Mode (LHM) capability
  • Low-power mode with wake from Ethernet, CAN, LIN, smart eFuses, and MSDI off-board switch inputs
  • Optimized microcontroller GPIO:
    • SPI daisy chain of smart eFuses and motor drivers
    • SPI and I2C IO expanders