SBOSA15
September 2022
TMP1827
ADVANCE INFORMATION
1
Features
2
Applications
3
Description
4
Revision History
5
Description (cont.)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
1-Wire Interface Timing
7.7
Security Engine Characteristics
7.8
EEPROM Characteristics
7.9
Timing Diagrams
7.10
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Power Up
8.3.2
Power Mode Switch
8.3.3
Bus Pullup Resistor
8.3.4
Temperature Results
8.3.5
Temperature Offset
8.3.6
Temperature Alert
8.3.7
Standard Device Address
8.3.7.1
Unique 64-Bit Device Address and ID
8.3.8
Flexible Device Address
8.3.8.1
Non-Volatile Short Address
8.3.8.2
IO Hardware Address
8.3.8.3
Resistor Address
8.3.8.4
Combined IO and Resistor Address
8.3.9
CRC Generation
8.3.10
Functional Register Map
8.3.11
User Memory Map
8.3.12
SHA-256-HMAC Authentication Block
8.3.13
Bit Communication
8.3.13.1
Host Write, Device Read
8.3.13.2
Host Read, Device Write
8.3.14
Bus Speed
8.3.15
NIST Traceability
8.4
Device Functional Modes
8.4.1
Conversion Modes
8.4.1.1
Basic One-Shot Conversion Mode
8.4.1.2
Auto Conversion Mode
8.4.1.3
Stacked Conversion Mode
8.4.1.4
Continuous Conversion Mode
8.4.2
Alert Function
8.4.2.1
Alert Mode
8.4.2.2
Comparator Mode
8.4.3
Single-Wire Interface Communication
8.4.3.1
Bus Reset Phase
8.4.3.2
Address Phase
8.4.3.2.1
READADDR (33h)
8.4.3.2.2
MATCHADDR (55h)
8.4.3.2.3
SEARCHADDR (F0h)
8.4.3.2.4
ALERTSEARCH (ECh)
8.4.3.2.5
SKIPADDR (CCh)
8.4.3.2.6
OVD SKIPADDR (3Ch)
8.4.3.2.7
OVD MATCHADDR (69h)
8.4.3.2.8
FLEXADDR (0Fh)
8.4.3.3
Function Phase
8.4.3.3.1
CONVERTTEMP (44h)
8.4.3.3.2
WRITE SCRATCHPAD-1 (4Eh)
8.4.3.3.3
READ SCRATCHPAD-1 (BEh)
8.4.3.3.4
COPY SCRATCHPAD-1 (48h)
8.4.3.3.5
WRITE SCRATCHPAD-2 (0Fh)
8.4.3.3.6
READ SCRATCHPAD-2 (AAh)
8.4.3.3.7
COPY SCRATCHPAD-2 (55h)
8.4.3.3.8
READ EEPROM (F0h)
8.4.3.3.9
GPIO WRITE (A5h)
8.4.3.3.10
GPIO READ (F5h)
8.4.4
NVM Operations
8.4.4.1
Programming User Data
8.4.4.2
Register and Memory Protection
8.4.4.2.1
Register Protection
8.4.4.2.2
User Memory Protection
8.5
Programming
8.5.1
Single Device Temperature Conversion and Read
8.5.2
Multiple Device Temperature Conversion and Read
8.5.3
Register Scratchpad Update and Commit
8.5.4
Single Device EEPROM Programming and Verify
8.5.5
Single Device EEPROM Lock Operation
8.5.6
Multiple Device IO Read
8.5.7
Multiple Device IO Write and Read
8.6
Register Maps
8.6.1
Temperature Result LSB Register (Scratchpad-1 offset = 00h) [reset = 00h]
8.6.2
Temperature Result MSB Register (Scratchpad-1 offset = 01h) [reset = 00h]
8.6.3
Status Register (Scratchpad-1 offset = 02h) [reset = 3Ch]
8.6.4
Device Configuration-1 Register (Scratchpad-1 offset = 04h) [reset = 70h]
8.6.5
Device Configuration-2 Register (Scratchpad-1 offset = 05h) [reset = 80h]
8.6.6
Short Address Register (Scratchpad-1 offset = 06h) [reset = 00h]
8.6.7
Temperature Alert Low LSB Register (Scratchpad-1 offset = 08h) [reset = 00h]
8.6.8
Temperature Alert Low MSB Register (Scratchpad-1 offset = 09h) [reset = 00h]
8.6.9
Temperature Alert High LSB Register (Scratchpad-1 offset = 0Ah) [reset = F0h]
8.6.10
Temperature Alert High MSB Register (Scratchpad-1 offset = 0Bh) [reset = 07h]
8.6.11
Temperature Offset LSB Register (Scratchpad-1 offset = 0Ch) [reset = 00h]
8.6.12
Temperature Offset MSB Register (Scratchpad-1 offset = 0Dh) [reset = 00h]
8.6.13
IO Read Register [reset = F0h]
8.6.14
IO Configuration Register [reset = 00h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Bus Powered Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.2
Supply Powered Application
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.3
UART Interface for Communication
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
11.1
Package Option Addendum
11.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
NGR|8
MPDS404A
Thermal pad, mechanical data (Package|Pins)
NGR|8
QFND688B
Orderable Information
sbosa15_oa
1
Features
Single-wire interface with multi-drop shared bus and CRC
Bus powered with operating voltage from 1.7 V to 5.5 V
IEC 61000-4-2 ESD for 8-kV contact discharge
High-accuracy digital temperature sensor:
±0.1°C (typical)/±0.3°C (maximum) from –20°C to +85°C
±0.3°C (typical)/±0.5°C (maximum) from –55°C to +125°C
±0.5°C (typical)/±1.0°C (maximum) from –55°C to +150°C
Active current of 100-µA (typical) and shutdown current of 1.0 µA (typical)
16-bit temperature resolution: 7.8125 m°C (1 LSB)
Fast data rates of 90 kbps in overdrive speed
Flexible user programmable short address modes for faster device address
SHA-256-HMAC authentication scheme
FIPS 180-4 compliant Secure Hash Implementation
FIPS 198-1 compliant HMAC Implementation
2-kbit EEPROM features:
Write operation in block size of 64-bits
Continuous read mode
Read with write protection with page size of 256-bits
Authenticated write protection mode with page size of 256-bits
Read/write current of 95 µA/178 µA (typical)
NIST traceable factory-programmed non erasable 64-bit identification number for device addressing
4 configurable open-drain digital input-output and temperature alert