SLUSEO6 may 2023 TPSM843B22

ADVANCE INFORMATION

Package Options

Mechanical Data (Package|Pins)

RDG|25
- MPQF603

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sluseo6_oa

1 Features

Fixed-frequency, internally compensated advanced current mode (ACM) control
Integrated 6.5-mΩ and 2-mΩ MOSFETs, Inductor and basic passives
4-V to 18-V input voltage range
0.5-V to 7-V output voltage range
True differential remote sense amplifier (RSA)
Three selectable PWM ramp options to optimize the control loop performance
Five selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz
Synchronizable to an external clock
0.5 V, ±0.5% voltage reference accuracy over full temperature range
1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start times
Monotonic start-up into prebiased outputs
Selectable current limits to support 20-A and 16-A operation
Enable with adjustable input undervoltage lockout
Power-good output monitor
Output overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection
–40°C to 125°C operating junction temperature
6.5-mm × 7.5-mm × 4.0-mm, 25-pin over-molded QFN package
Lead-free (RoHS compliant) SLUSEO6-TPSM843x2x TPSM843B22 4-V to 18-V Input, 20-A, Buck Power Module with Internally Compensated, Advanced, Current Mode Control TPSM843B22 4-V to 18-V Input, 20-A, Buck Power Module with Internally Compensated, Advanced, Current Mode Control Features Features Applications Applications Description Description Table of Contents Table of Contents Revision History Revision History Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description VIN Pins and VIN UVLO VIN Pins and VIN UVLO Internal Bypassing (BP5) Internal Bypassing (BP5) Enable and Adjustable UVLO Enable and Adjustable UVLO Internal Sequence of Events During Start-up Internal Sequence of Events During Start-up Switching Frequency Selection Switching Frequency Selection Switching Frequency Synchronization to an External Clock Switching Frequency Synchronization to an External Clock Internal PWM Oscillator Frequency Internal PWM Oscillator Frequency Loss of Synchronization Loss of Synchronization Interfacing the SYNC/FSEL Pin Interfacing the SYNC/FSEL Pin Remote Sense Amplifier and Adjusting the Output Voltage Remote Sense Amplifier and Adjusting the Output Voltage Loop Compensation Guidelines Loop Compensation Guidelines Output Filter Inductor Tradeoffs Output Filter Inductor Tradeoffs Ramp Capacitor Selection Ramp Capacitor Selection Output Capacitor Selection Output Capacitor Selection Design Method for Good Transient Response Design Method for Good Transient Response Soft Start and Prebiased Output Start-up Soft Start and Prebiased Output Start-up MSEL Pin MSEL Pin Power Good (PG) Power Good (PG) Output Overload Protection Output Overload Protection Positive Inductor Current Protection Positive Inductor Current Protection Negative Inductor Current Protection Negative Inductor Current Protection Output Overvoltage and Undervoltage Protection Output Overvoltage and Undervoltage Protection Overtemperature Protection Overtemperature Protection Output Voltage Discharge Output Voltage Discharge Device Functional Modes Device Functional Modes Forced Continuous-Conduction Mode Forced Continuous-Conduction Mode Discontinuous Conduction Mode During Soft Start Discontinuous Conduction Mode During Soft Start Application and Implementation Application and Implementation Application Information Application Information Typical Applications Typical Applications 1.0-V Output, 1-MHz Application 1.0-V Output, 1-MHz Application Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Switching Frequency Switching Frequency Output Inductor Selection Output Inductor Selection Output Capacitor Output Capacitor Input Capacitor Input Capacitor Adjustable Undervoltage Lockout Adjustable Undervoltage Lockout Output Voltage Resistors Selection Output Voltage Resistors Selection Bootstrap Capacitor Selection Bootstrap Capacitor Selection BP5 Capacitor Selection BP5 Capacitor Selection PG Pullup Resistor PG Pullup Resistor Current Limit Selection Current Limit Selection Soft-Start Time Selection Soft-Start Time Selection Ramp Selection and Control Loop Stability Ramp Selection and Control Loop Stability MSEL Pin MSEL Pin Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Thermal Performance Thermal Performance Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information Tape and Reel Information Tape and Reel Information IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER TPSM843B22 4-V to 18-V Input, 20-A, Buck Power Module with Internally Compensated, Advanced, Current Mode Control TPSM843B22 4-V to 18-V Input, 20-A, Buck Power Module with Internally Compensated, Advanced, Current Mode ControlTPSM843B2220 Features A Changed status from Advance Information to Production Data yes A First public release yes Fixed-frequency, internally compensated advanced current mode (ACM) control Integrated 6.5-mΩ and 2-mΩ MOSFETs, Inductor and basic passives 4-V to 18-V input voltage range 0.5-V to 7-V output voltage range True differential remote sense amplifier (RSA) Three selectable PWM ramp options to optimize the control loop performance Five selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz Synchronizable to an external clock 0.5 V, ±0.5% voltage reference accuracy over full temperature range 1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start times Monotonic start-up into prebiased outputs Selectable current limits to support 20-A and 16-A operation Enable with adjustable input undervoltage lockout Power-good output monitor Output overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection –40°C to 125°C operating junction temperature 6.5-mm × 7.5-mm × 4.0-mm, 25-pin over-molded QFN package Lead-free (RoHS compliant) Pin compatible with the 16 A - TPSM843A26 and 12 A - TPSM843A22 Features A Changed status from Advance Information to Production Data yes A First public release yes A Changed status from Advance Information to Production Data yes A First public release yes A Changed status from Advance Information to Production Data yes AChanged status from Advance Information to Production Datayes A First public release yes AFirst public releaseyes Fixed-frequency, internally compensated advanced current mode (ACM) control Integrated 6.5-mΩ and 2-mΩ MOSFETs, Inductor and basic passives 4-V to 18-V input voltage range 0.5-V to 7-V output voltage range True differential remote sense amplifier (RSA) Three selectable PWM ramp options to optimize the control loop performance Five selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz Synchronizable to an external clock 0.5 V, ±0.5% voltage reference accuracy over full temperature range 1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start times Monotonic start-up into prebiased outputs Selectable current limits to support 20-A and 16-A operation Enable with adjustable input undervoltage lockout Power-good output monitor Output overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection –40°C to 125°C operating junction temperature 6.5-mm × 7.5-mm × 4.0-mm, 25-pin over-molded QFN package Lead-free (RoHS compliant) Pin compatible with the 16 A - TPSM843A26 and 12 A - TPSM843A22 Fixed-frequency, internally compensated advanced current mode (ACM) control Integrated 6.5-mΩ and 2-mΩ MOSFETs, Inductor and basic passives 4-V to 18-V input voltage range 0.5-V to 7-V output voltage range True differential remote sense amplifier (RSA) Three selectable PWM ramp options to optimize the control loop performance Five selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz Synchronizable to an external clock 0.5 V, ±0.5% voltage reference accuracy over full temperature range 1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start times Monotonic start-up into prebiased outputs Selectable current limits to support 20-A and 16-A operation Enable with adjustable input undervoltage lockout Power-good output monitor Output overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection –40°C to 125°C operating junction temperature 6.5-mm × 7.5-mm × 4.0-mm, 25-pin over-molded QFN package Lead-free (RoHS compliant) Pin compatible with the 16 A - TPSM843A26 and 12 A - TPSM843A22 Fixed-frequency, internally compensated advanced current mode (ACM) control Integrated 6.5-mΩ and 2-mΩ MOSFETs, Inductor and basic passives 4-V to 18-V input voltage range 0.5-V to 7-V output voltage range True differential remote sense amplifier (RSA) Three selectable PWM ramp options to optimize the control loop performance Five selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHz Synchronizable to an external clock 0.5 V, ±0.5% voltage reference accuracy over full temperature range 1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start times Monotonic start-up into prebiased outputs Selectable current limits to support 20-A and 16-A operation Enable with adjustable input undervoltage lockout Power-good output monitor Output overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection –40°C to 125°C operating junction temperature 6.5-mm × 7.5-mm × 4.0-mm, 25-pin over-molded QFN package Lead-free (RoHS compliant) Pin compatible with the 16 A - TPSM843A26 and 12 A - TPSM843A22 Fixed-frequency, internally compensated advanced current mode (ACM) controlIntegrated 6.5-mΩ and 2-mΩ MOSFETs, Inductor and basic passives4-V to 18-V input voltage range0.5-V to 7-V output voltage rangeTrue differential remote sense amplifier (RSA)Three selectable PWM ramp options to optimize the control loop performanceFive selectable switching frequencies: 500 kHz, 750 kHz, 1 MHz, 1.5 MHz, and 2.2 MHzSynchronizable to an external clock0.5 V, ±0.5% voltage reference accuracy over full temperature range1-ms, 2-ms, 4-ms, and 8-ms selectable soft-start timesMonotonic start-up into prebiased outputsSelectable current limits to support 20-A and 16-A operation2016Enable with adjustable input undervoltage lockoutPower-good output monitorOutput overvoltage, output undervoltage, input undervoltage, overcurrent, and overtemperature protection–40°C to 125°C operating junction temperature6.5-mm × 7.5-mm × 4.0-mm, 25-pin over-molded QFN package Lead-free (RoHS compliant) Pin compatible with the 16 A - TPSM843A26 and 12 A - TPSM843A22 16 A - TPSM843A26 and 12 A - TPSM843A22TPSM843A26 Applications Wireless and wired communications infrastructure equipment Optical and fiber networks Test and measurement Medical and healthcare Applications Wireless and wired communications infrastructure equipment Optical and fiber networks Test and measurement Medical and healthcare Wireless and wired communications infrastructure equipment Optical and fiber networks Test and measurement Medical and healthcare Wireless and wired communications infrastructure equipment Optical and fiber networks Test and measurement Medical and healthcare Wireless and wired communications infrastructure equipment Wireless and wired communications infrastructure equipment Optical and fiber networks Optical and fiber networks Test and measurement Test and measurement Medical and healthcare Medical and healthcare Description The TPSM843B22 is a high-efficiency 18-V, 20-A synchronous buck module employing an internally compensated, fixed-frequency advanced current mode (ACM) control architecture, which while always operating under FCCM, generates output voltages from 0.5 V to 7 V. The module is capable of providing high efficiency while operating at a switching frequency up to 2.2 MHz. The module is in a 6.5-mm x 7.5-mm x 4-mm over-molded package, which makes it optimal for designs requiring a small solution size. Additional features include a high accuracy voltage reference, selectable soft-start times, monotonic start-up into prebiased outputs, selectable current limits, adjustable UVLO through the EN pin, and a full suite of fault protections. Package Information Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm For all available packages, see the orderable addendum at the end of the data sheet. TPSM843B22 Simplified Application Typical Application Efficiency Description The TPSM843B22 is a high-efficiency 18-V, 20-A synchronous buck module employing an internally compensated, fixed-frequency advanced current mode (ACM) control architecture, which while always operating under FCCM, generates output voltages from 0.5 V to 7 V. The module is capable of providing high efficiency while operating at a switching frequency up to 2.2 MHz. The module is in a 6.5-mm x 7.5-mm x 4-mm over-molded package, which makes it optimal for designs requiring a small solution size. Additional features include a high accuracy voltage reference, selectable soft-start times, monotonic start-up into prebiased outputs, selectable current limits, adjustable UVLO through the EN pin, and a full suite of fault protections. Package Information Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm For all available packages, see the orderable addendum at the end of the data sheet. TPSM843B22 Simplified Application Typical Application Efficiency The TPSM843B22 is a high-efficiency 18-V, 20-A synchronous buck module employing an internally compensated, fixed-frequency advanced current mode (ACM) control architecture, which while always operating under FCCM, generates output voltages from 0.5 V to 7 V. The module is capable of providing high efficiency while operating at a switching frequency up to 2.2 MHz. The module is in a 6.5-mm x 7.5-mm x 4-mm over-molded package, which makes it optimal for designs requiring a small solution size. Additional features include a high accuracy voltage reference, selectable soft-start times, monotonic start-up into prebiased outputs, selectable current limits, adjustable UVLO through the EN pin, and a full suite of fault protections. The TPSM843B22 is a high-efficiency 18-V, 20-A synchronous buck module employing an internally compensated, fixed-frequency advanced current mode (ACM) control architecture, which while always operating under FCCM, generates output voltages from 0.5 V to 7 V. The module is capable of providing high efficiency while operating at a switching frequency up to 2.2 MHz. The module is in a 6.5-mm x 7.5-mm x 4-mm over-molded package, which makes it optimal for designs requiring a small solution size. Additional features include a high accuracy voltage reference, selectable soft-start times, monotonic start-up into prebiased outputs, selectable current limits, adjustable UVLO through the EN pin, and a full suite of fault protections.TPSM843B2220 Package Information Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm For all available packages, see the orderable addendum at the end of the data sheet. Package Information Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm Package Information Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) Part Number Package#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE Body Size (NOM) Part NumberPackage#GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTE #GUID-BE398179-F43A-420F-B130-302625A52ECA/DEVINFONOTEBody Size (NOM) TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm TPSM843B22 RDG (B3QFN-RDG, 25) 6.50 mm × 7.50 mm TPSM843B22 TPSM843B22RDG (B3QFN-RDG, 25)6.50 mm × 7.50 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. TPSM843B22 Simplified Application Typical Application Efficiency TPSM843B22 Simplified Application Typical Application Efficiency TPSM843B22 Simplified Application TPSM843B22 Simplified ApplicationTPSM843B22 Typical Application Efficiency Typical Application Efficiency Table of Contents yes Table of Contents yes yes yes Revision History DATE REVISION NOTES * Initial Release Revision History DATE REVISION NOTES * Initial Release DATE REVISION NOTES * Initial Release DATE REVISION NOTES * Initial Release DATE REVISION NOTES * Initial Release DATE REVISION NOTES DATE REVISION NOTES DATEREVISIONNOTES * Initial Release * Initial Release *Initial Release Pin Configuration and Functions 25-Pin B3QFN-RDG Package (Bottom View) 25-Pin B3QFN-RDG Package
(Top View) Pin Functions Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description Name No. VOUT 1,20 O Output voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. I = input, O = output, P = Supply, G = ground Pin Configuration and Functions 25-Pin B3QFN-RDG Package (Bottom View) 25-Pin B3QFN-RDG Package
(Top View) Pin Functions Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description Name No. VOUT 1,20 O Output voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. I = input, O = output, P = Supply, G = ground 25-Pin B3QFN-RDG Package (Bottom View) 25-Pin B3QFN-RDG Package
(Top View) Pin Functions Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description Name No. VOUT 1,20 O Output voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. I = input, O = output, P = Supply, G = ground 25-Pin B3QFN-RDG Package (Bottom View) 25-Pin B3QFN-RDG Package
(Top View) 25-Pin B3QFN-RDG Package (Bottom View) 25-Pin B3QFN-RDG Package (Bottom View) 25-Pin B3QFN-RDG Package
(Top View) 25-Pin B3QFN-RDG Package
(Top View) Pin Functions Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description Name No. VOUT 1,20 O Output voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. Pin Functions Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description Name No. VOUT 1,20 O Output voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description Name No. Pin Type#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B Description PinType#GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5B #GUID-A2603E83-61D8-492A-BDD0-B3BC71AECFDD/LI_FMM_NCX_R5BDescription Name No. NameNo. VOUT 1,20 O Output voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. VOUT 1,20 O Output voltage for the converter VOUT1,20OOutput voltage for the converter FB 2 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. FB FB2IFeedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage. GOSNS 3 I Ground sense return and input to the differential remote sense amplifier. GOSNS3IGround sense return and input to the differential remote sense amplifier. AGND 4 G Analog ground return AGND4GAnalog ground return BP5 5 — Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. BP55—Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module. VIN 6,7,14,15,23 P Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. VIN6,7,14,15,23PInput power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended. PGND 8,9,12,13,21,22,24,25 G Ground return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. PGND8,9,12,13,21,22,24,25GGround return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB. SW 10 O Switch node of the converter. Leave this pin floating. SW10OSwitch node of the converter. Leave this pin floating. BOOT 11 I Supply for the internal high-side MOSFET gate driver. Leave this pin floating. BOOT11ISupply for the internal high-side MOSFET gate driver. Leave this pin floating. EN 16 I Enable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. EN16IEnable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors. PG 17 O Open drain power-good indicator PG17OOpen drain power-good indicator SYNC/FSEL 18 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. SYNC/FSEL18IFrequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. MSEL 19 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. MSEL19IA resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings. I = input, O = output, P = Supply, G = ground I = input, O = output, P = Supply, G = ground Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/ABSMAXNOTE_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/SFVG2_ZW7MD3 MIN MAX UNIT Pin voltage VIN –0.3 20 V Pin Voltage VOUT –0.3 7 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage BP5 –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG Pin Current Sink Capability mA Peak Reflow Case Temperature 250 °C Number of reflows allowed 2 TJ Operating junction temperature –40 125 °C Tstg –55 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to PGND. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 20 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 125 °C Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT RDG (BGQFN) 25 PINS RθJA Junction-to-ambient thermal resistance 21.6 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Electrical Characteristics TJ = –40°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing current VEN = 1.3 V 11.6 µA REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 37 ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG threshold VFB falling (Good) 105 108 111 % VREF PG threshold VFB falling (UV Fault) 81 84 87 % VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V Min VIN for valid PG output 1 V PG delay going from low to high 256 us PG delay going from high to low 8 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C Specified by design Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/ABSMAXNOTE_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/SFVG2_ZW7MD3 MIN MAX UNIT Pin voltage VIN –0.3 20 V Pin Voltage VOUT –0.3 7 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage BP5 –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG Pin Current Sink Capability mA Peak Reflow Case Temperature 250 °C Number of reflows allowed 2 TJ Operating junction temperature –40 125 °C Tstg –55 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to PGND. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/ABSMAXNOTE_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/SFVG2_ZW7MD3 MIN MAX UNIT Pin voltage VIN –0.3 20 V Pin Voltage VOUT –0.3 7 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage BP5 –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG Pin Current Sink Capability mA Peak Reflow Case Temperature 250 °C Number of reflows allowed 2 TJ Operating junction temperature –40 125 °C Tstg –55 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to PGND. over operating free-air temperature range (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/ABSMAXNOTE_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/SFVG2_ZW7MD3 MIN MAX UNIT Pin voltage VIN –0.3 20 V Pin Voltage VOUT –0.3 7 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage BP5 –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG Pin Current Sink Capability mA Peak Reflow Case Temperature 250 °C Number of reflows allowed 2 TJ Operating junction temperature –40 125 °C Tstg –55 150 °C over operating free-air temperature range (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/ABSMAXNOTE_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/SFVG2_ZW7MD3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/ABSMAXNOTE_SF1#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280995/SFVG2_ZW7MD3 MIN MAX UNIT Pin voltage VIN –0.3 20 V Pin Voltage VOUT –0.3 7 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage BP5 –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG Pin Current Sink Capability mA Peak Reflow Case Temperature 250 °C Number of reflows allowed 2 TJ Operating junction temperature –40 125 °C Tstg –55 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Pin voltage VIN –0.3 20 V Pin Voltage VOUT –0.3 7 V Pin voltage SW, DC –0.3 20 V Pin voltage SW, transient 20ns –5 22 V Pin voltage VIN to SW, DC –0.3 20 V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltage BOOT –0.3 25 V Pin voltage BOOT to SW –0.3 6 V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltage BP5 –0.3 6 V Pin voltage GOSNS –0.3 0.3 V Sink current PG Pin Current Sink Capability mA Peak Reflow Case Temperature 250 °C Number of reflows allowed 2 TJ Operating junction temperature –40 125 °C Tstg –55 150 °C Pin voltage VIN –0.3 20 V Pin voltageVIN–0.320V Pin Voltage VOUT –0.3 7 V Pin VoltageVOUT –0.37V Pin voltage SW, DC –0.3 20 V Pin voltageSW, DC–0.320V Pin voltage SW, transient 20ns –5 22 V Pin voltageSW, transient 20ns–522V Pin voltage VIN to SW, DC –0.3 20 V Pin voltageVIN to SW, DC–0.320V Pin voltage VIN to SW, transient 20ns –6 25 V Pin voltageVIN to SW, transient 20ns–625V Pin voltage BOOT –0.3 25 V Pin voltageBOOT–0.325V Pin voltage BOOT to SW –0.3 6 V Pin voltageBOOT to SW–0.36V Pin voltage EN, PG, MSEL, SYNC/FSEL, FB –0.3 6 V Pin voltageEN, PG, MSEL, SYNC/FSEL, FB–0.36V Pin voltage BP5 –0.3 6 V Pin voltageBP5–0.36V Pin voltage GOSNS –0.3 0.3 V Pin voltageGOSNS–0.30.3V Sink current PG Pin Current Sink Capability mA Sink currentPG Pin Current Sink CapabilitymA Peak Reflow Case Temperature 250 °C Peak Reflow Case Temperature250°C Number of reflows allowed 2 Number of reflows allowed2 TJ Operating junction temperature –40 125 °C TJ JOperating junction temperature –40125°C Tstg –55 150 °C Tstg stg–55150°C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to PGND. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.All voltage values are with respect to PGND. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/HBM_COMM1±2000V V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 ±500 V V(ESD) (ESD)Electrostatic dischargeCharged-device model (CDM), per ANSI/ESDA/JEDEC JS-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280968/CDM_COMM1±500V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 20 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 125 °C Recommended Operating Conditions Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 20 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 125 °C Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 20 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 125 °C Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 20 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VIN Pin voltage Input voltage range 4 18 V VOUT Output voltage range Output voltage range 0.5 7 V Pin voltage SW - PGND –0.1 18 V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltage GOSNS –0.3 0.3 V IOUT Output current range 20 A IPG Power Good input current 2 5 mA TJ Operating junction temperature Operating junction temperature –40 125 °C VIN Pin voltage Input voltage range 4 18 V VIN INPin voltageInput voltage range418V VOUT Output voltage range Output voltage range 0.5 7 V VOUT OUTOutput voltage rangeOutput voltage range 0.57V Pin voltage SW - PGND –0.1 18 V Pin voltageSW - PGND–0.118V Pin voltage EN, FB, PG, MSEL, SYNC/FSEL –0.1 5.5 V Pin voltageEN, FB, PG, MSEL, SYNC/FSEL–0.15.5V Pin voltage GOSNS –0.3 0.3 V Pin voltageGOSNS–0.30.3V IOUT Output current range 20 A IOUT OUTOutput current range20A IPG Power Good input current 2 5 mA IPG PGPower Good input current25mA TJ Operating junction temperature Operating junction temperature –40 125 °C TJ JOperating junction temperatureOperating junction temperature–40125°C Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT RDG (BGQFN) 25 PINS RθJA Junction-to-ambient thermal resistance 21.6 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT RDG (BGQFN) 25 PINS RθJA Junction-to-ambient thermal resistance 21.6 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT RDG (BGQFN) 25 PINS RθJA Junction-to-ambient thermal resistance 21.6 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT RDG (BGQFN) 25 PINS RθJA Junction-to-ambient thermal resistance 21.6 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT RDG (BGQFN) 25 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 TPSM843B22 TPSM843A26 TPSM843A22 UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281061/APPNOTE_SPRA953TPSM843B22 TPSM843A26 TPSM843A22UNIT RDG (BGQFN) RDG (BGQFN) 25 PINS 25 PINS RθJA Junction-to-ambient thermal resistance 21.6 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W RθJA Junction-to-ambient thermal resistance 21.6 °C/W RθJA θJAJunction-to-ambient thermal resistance21.6°C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJT JTJunction-to-top characterization parameter7.5°C/W ψJB Junction-to-board characterization parameter 13.0 °C/W ψJB JBJunction-to-board characterization parameter13.0°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal Metrics Electrical Characteristics TJ = –40°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing current VEN = 1.3 V 11.6 µA REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 37 ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG threshold VFB falling (Good) 105 108 111 % VREF PG threshold VFB falling (UV Fault) 81 84 87 % VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V Min VIN for valid PG output 1 V PG delay going from low to high 256 us PG delay going from high to low 8 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C Specified by design Electrical Characteristics TJ = –40°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing current VEN = 1.3 V 11.6 µA REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 37 ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG threshold VFB falling (Good) 105 108 111 % VREF PG threshold VFB falling (UV Fault) 81 84 87 % VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V Min VIN for valid PG output 1 V PG delay going from low to high 256 us PG delay going from high to low 8 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C Specified by design TJ = –40°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing current VEN = 1.3 V 11.6 µA REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 37 ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG threshold VFB falling (Good) 105 108 111 % VREF PG threshold VFB falling (UV Fault) 81 84 87 % VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V Min VIN for valid PG output 1 V PG delay going from low to high 256 us PG delay going from high to low 8 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C TJ = –40°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted) TJ = –40°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted) JVIN PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing current VEN = 1.3 V 11.6 µA REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 37 ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG threshold VFB falling (Good) 105 108 111 % VREF PG threshold VFB falling (UV Fault) 81 84 87 % VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V Min VIN for valid PG output 1 V PG delay going from low to high 256 us PG delay going from high to low 8 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(H) VIN UVLO hysteresis 150 mV INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(H) EN voltage hysteresis 100 mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing current VEN = 1.3 V 11.6 µA REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIL(sync) Low-level input voltage 0.8 V SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V TON(min) Minimum ON pulse width 22 37 ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(NOC) Low-side negative current limit Current into SW pin 7 A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG threshold VFB falling (Good) 105 108 111 % VREF PG threshold VFB falling (UV Fault) 81 84 87 % VREF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V Min VIN for valid PG output 1 V PG delay going from low to high 256 us PG delay going from high to low 8 µs HICCUP Hiccup time before re-start 7*tSS ms OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C SUPPLY VOLTAGE SUPPLY VOLTAGE IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA IQ(VIN) Q(VIN)VIN operating non-switching supply currentVEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHzENFBVIN12001600µA ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA ISD(VIN) SD(VIN)VIN shutdown supply currentVEN = 0 V, VVIN = 12 VENVIN1525µA VINUVLO(R) VIN UVLO rising threshold VIN rising 3.9 4.00 4.1 V VINUVLO(R) UVLO(R)VIN UVLO rising thresholdVIN risingIN3.94.004.1V VINUVLO(H) VIN UVLO hysteresis 150 mV VINUVLO(H) UVLO(H)VIN UVLO hysteresis150mV INTERNAL LDO INTERNAL LDO BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V BP5Internal LDO output voltageVVIN = 12 V, IVBP5 = 25 mAVIN VBP5 4.5V Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV Internal LDO dropout voltageVVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mAVINVBP5VIN VBP5 350mV Internal LDO short-circuit current limit VVIN = 12 V 177 mA Internal LDO short-circuit current limitVVIN = 12 VVIN 177mA ENABLE ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V VEN(R) EN(R)EN voltage rising thresholdEN rising, enable switching1.21.25V VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V VEN(F) EN(F)EN voltage falling thresholdEN falling, disable switching1.051.1V VEN(H) EN voltage hysteresis 100 mV VEN(H) EN(H)EN voltage hysteresis100mV EN pin sourcing current VEN = 1.1 V 1.5 µA EN pin sourcing currentVEN = 1.1 VEN1.5µA EN pin sourcing current VEN = 1.3 V 11.6 µA EN pin sourcing currentVEN = 1.3 VEN11.6µA REFERENCE VOLTAGE REFERENCE VOLTAGE VFB Feedback Voltage TJ = –40°C to 125°C 495 500 505 mV VFB FBFeedback Voltage TJ = –40°C to 125°CJ495500505mV IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA IFB(LKG) FB(LKG)Input leakage current into FB pinVFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 VFBVINEN1nA REMOTE SENSE AMPLIFIER REMOTE SENSE AMPLIFIER ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA ILEAK(GOSNS) LEAK(GOSNS)Current out of GOSNS pin859095µA VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV VIRNG(GOSNS) IRNG(GOSNS)GOSNS common mode voltage for regulationAGND +/- VGOSNS GOSNS–100100mV SWITCHING FREQUENCY AND OSCILLATOR SWITCHING FREQUENCY AND OSCILLATOR fSW Switching frequency RFSEL = 24.3 kΩ to AGND 450 500 550 kHz fSW SWSwitching frequencyRFSEL = 24.3 kΩ to AGND FSEL450500550kHz fSW Switching frequency RFSEL = 17.4 kΩ to AGND 675 750 825 kHz fSW SWSwitching frequencyRFSEL = 17.4 kΩ to AGND FSEL675750825kHz fSW Switching frequency RFSEL = 11.8 kΩ to AGND 900 1000 1100 kHz fSW SWSwitching frequencyRFSEL = 11.8 kΩ to AGND FSEL90010001100kHz fSW Switching frequency RFSEL = 8.06 kΩ to AGND 1350 1500 1650 kHz fSW SWSwitching frequencyRFSEL = 8.06 kΩ to AGND FSEL135015001650kHz fSW Switching frequency RFSEL = 4.99 kΩ to AGND 1980 2200 2420 kHz fSW SWSwitching frequencyRFSEL = 4.99 kΩ to AGND FSEL198022002420kHz SYNCHRONIZATION SYNCHRONIZATION VIH(sync) High-level input voltage 1.8 V VIH(sync) IH(sync)High-level input voltage1.8V VIL(sync) Low-level input voltage 0.8 V VIL(sync) IL(sync)Low-level input voltage0.8V SOFT-START SOFT-START tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms tSS1 SS1Soft-start timeRMSEL = 1.78 kΩMSEL1ms tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms tSS2 SS2Soft-start timeRMSEL = 2.21 kΩMSEL2ms tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms tSS3 SS3Soft-start timeRMSEL = 2.74 kΩMSEL4ms tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms tSS4 SS4Soft-start timeRMSEL = 3.32 kΩMSEL8ms POWER STAGE POWER STAGE RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ RDS(on)HS DS(on)HSHigh-side MOSFET on-resistanceTJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 VJ VINBOOT-SW6.5mΩ RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ RDS(on)LS DS(on)LSLow-side MOSFET on-resistanceTJ = 25°C, VBP5 = 4.5 VJ 2.0mΩ VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V VVIN(TH_r) VIN(TH_r)VIN throttle rising thresholdTJ = 25°C. Weaken high-side gate drive upon VIN risingJ 16V VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V VVIN(TH_f) VIN(TH_f)VIN throttle falling thresholdTJ = 25°C. Recover high-side gate drive upon VIN fallingJ 15.5V VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V VBOOT-SW(UV_R) BOOT-SW(UV_R)BOOT-SW UVLO rising thresholdVBOOT-SW risingBOOT-SW3.2V VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V VBOOT-SW(UV_F) BOOT-SW(UV_F)BOOT-SW UVLO falling thresholdVBOOT-SW fallingBOOT-SW2.8V TON(min) Minimum ON pulse width 22 37 ns TON(min) ON(min)Minimum ON pulse width2237ns TOFF(min) Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 115 ns TOFF(min) OFF(min)Minimum OFF pulse width #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266115ns CURRENT SENSE AND OVERCURRENT PROTECTION CURRENT SENSE AND OVERCURRENT PROTECTION IHS(OC1) High-side peak current limit (B22) RMSEL = 2.1 kΩ 26.1 29 31.9 A IHS(OC1) HS(OC1)High-side peak current limit (B22)RMSEL = 2.1 kΩMSEL26.12931.9A IHS(OC2) RMSEL = 22.1 kΩ 20.7 23 25.3 A IHS(OC2) HS(OC2)RMSEL = 22.1 kΩMSEL20.72325.3A ILS(OC1) Low-side valley current limit (B22) RMSEL = 2.1 kΩ 19.8 22 24.2 A ILS(OC1) LS(OC1)Low-side valley current limit (B22)RMSEL = 2.1 kΩMSEL19.82224.2A ILS(OC2) RMSEL = 22.1 kΩ 15.84 17.6 19.36 A ILS(OC2) LS(OC2)RMSEL = 22.1 kΩMSEL15.8417.619.36A ILS(NOC) Low-side negative current limit Current into SW pin 7 A ILS(NOC) LS(NOC)Low-side negative current limitCurrent into SW pin7A OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF VOVP OVPOvervoltage-protection (OVP) threshold voltageVFB risingFB120% VREF REF VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF VUVP UVPUndervoltage-protection (UVP) threshold voltageVFB fallingFB80% VREF REF PG (Power Good) PG (Power Good) PG threshold VFB rising (Good) 89 92 95 % VREF PG thresholdVFB rising (Good)FB899295% VREF REF PG threshold VFB rising (OV Fault) 113 116 119 % VREF PG thresholdVFB rising (OV Fault)FB113116119% VREF REF PG threshold VFB falling (Good) 105 108 111 % VREF PG thresholdVFB falling (Good)FB105108111% VREF REF PG threshold VFB falling (UV Fault) 81 84 87 % VREF PG thresholdVFB falling (UV Fault)FB818487% VREF REF IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA IPG(LKG) PG(LKG)Leakage current into PG pin when open drain output is highVPG = 4.7 VPG 5µA VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V VPG(low) PG(low)PG low-level output voltageIPG = 2 mA, VIN = 12 VPG IN0.5V Min VIN for valid PG output 1 V Min VIN for valid PG output1V PG delay going from low to high 256 us PG delay going from low to high256us PG delay going from high to low 8 µs PG delay going from high to low8µs HICCUP HICCUP Hiccup time before re-start 7*tSS ms Hiccup time before re-start7*tSS SSms OUTPUT DISCHARGE OUTPUT DISCHARGE RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω RDischg DischgOutput discharge resistanceVVIN = 12 V, VSW = 0.5 V, power conversion disabled.VINSW100Ω THERMAL SHUTDOWN THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 Temperature rising 165 °C TJ(SD) J(SD)Thermal shutdown threshold #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266Temperature rising165°C TJ(HYS) Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 30 °C TJ(HYS) J(HYS)Thermal shutdown hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS48266 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000280971/SLUSBS4826630°C Specified by design Specified by design Detailed Description Overview The TPSM843B22 is a 20-A, high-performance, synchronous buck module with two integrated N-channel MOSFETs, inductor, and several passives. The TPSM843B22 has a maximum operating junction temperature of 125°C, making it designed for high-ambient temperature applications such as wireless infrastructure, wired optical modules and test and measurement applications. The input voltage range is 4 V to 18 V and the output voltage range is 0.5 V to 7 V. The module features a fixed-frequency advanced current mode (ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter components. The switching frequency of the device can be synchronized to an external clock applied to the FSEL/SYNC pin. Advanced current mode is an emulated peak current-mode control topology, supporting stable static and transient operation without the requirement for a complex external compensation design. ACM includes an internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-noise ratio for good noise immunity. The TPSM843B22 has three ramp options to optimize the internal feedback loop for various inductor and output capacitor combinations with only a single resistor to AGND (see for details). The TPSM843B22 is easy to use and allows low external component count with fast load transient response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise. Functional Block Diagram Feature Description VIN Pins and VIN UVLO The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV. A second means to enable the device is provided by interfacing to the EN pin. See for more details. Internal Bypassing (BP5) The BP5 pin is the bypass pin for internal analog circuitry. This pin is connected internally to the VCC and VDRV pins of the converter with internal bypass capacitors of 0.1 μF to VCC and 2.2 μF to VDRV pins of the internal converter. This pin is bypassed internally and no external bypassing is required. Enable and Adjustable UVLO The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin. Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in . The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using and . When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage. Adjustable UVLO Using EN Internal Sequence of Events During Start-up The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. Internal Start-up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). Switching Frequency Selection The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in #GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001. Use a 1% tolerance resistor or better. Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 Switching Frequency Synchronization to an External Clock The TPSM843B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See . Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. Internal PWM Oscillator Frequency When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 Loss of Synchronization If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition Interfacing the SYNC/FSEL Pin If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA. Interfacing the SYNC/FSEL Pin with a Buffer Remote Sense Amplifier and Adjusting the Output Voltage Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load. The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as shown in . Use 1% tolerance or better divider resistors. FB Resistor Divider Starting with a fixed value for the bottom resistor, typically 10 kΩ, use to calculate the top resistor in the divider. Loop Compensation Guidelines The TPSM843B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections. Output Filter Inductor Tradeoffs The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. Ramp Capacitor Selection The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in . Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application. First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings Output Capacitor Selection Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Design Method for Good Transient Response The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. Soft Start and Prebiased Output Start-up During start-up, the device softly increases the reference voltage from zero to its final value, thereby reducing converter inrush current. There are four options for the soft-start time, which is the time it takes for the reference to ramp to 0.5 V: 1 ms 2 ms 4 ms 8 ms The soft-start time is selected with a resistor to AGND on the MSEL pin. See . If a prebiased output condition exists prior to start-up, the device prevents current from being discharged from the output. During monotonic prebiased start-up, the low-side MOSFET is not allowed to sink current until the SS pin voltage is higher than the FB pin voltage and the high-side MOSFET begins to switch. The one exception is if the BOOT-SW voltage is below its UVLO threshold. While in BOOT-SW UVLO, the low-side MOSFET is allowed to turn on to charge the BOOT capacitor. The low-side MOSFET reverse current protection provides another layer of protection for the device after the high-side MOSFET begins to switch. MSEL Pin The ramp amplitude, soft-start time, and current limit settings are programmed with a single resistor, RMSEL, from MSEL to AGND. #GUID-AE26DD20-5F78-4B29-B9E7-9BEBDB0372D3/TB001004 lists the resistor values for the available options. Use a 1% tolerance resistor or better. See for the corresponding current limit thresholds for the "High" and "Low" settings. MSEL Pin Selection RMSEL (kΩ) Current Limits CRAMP (pF) Soft-Start Time (ms) 1.78 High 1 1 2.21 High 1 2 2.74 High 1 4 3.32 High 1 8 4.02 High 2 1 4.87 High 2 2 5.9 High 2 4 7.32 High 2 8 9.09 High 4 1 11.3 High 4 2 14.3 High 4 4 18.2 High 4 8 22.1 Low 1 1 26.7 Low 1 2 33.2 Low 1 4 40.2 Low 1 8 49.9 Low 2 1 60.4 Low 2 2 76.8 Low 2 4 102 Low 2 8 137 Low 4 1 174 Low 4 2 243 Low 4 4 412 Low 4 8 Power Good (PG) The TPSM843B22 PG pin is an open-drain output requiring an external pullup resistor to output a high signal. After the FB pin is between 92% and 108% of the internal voltage reference, soft start is complete, and after a 256-µs deglitch time, the PG pin is de-asserted and the pin floats. TI recommends a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. PG is in a defined state after the VIN input voltage is greater than 1 V but with reduced current sinking capability. When the FB is lower than 84% or greater than 116% of the nominal internal reference voltage, after a 8-µs deglitch time, the PG pin is pulled low. PG is immediately pulled low if VIN falls below its UVLO, the EN pin is pulled low or the device enters thermal shutdown. Output Overload Protection The TPSM843B22 protects against output overload (that is, overcurrent) events by cycle-by-cycle current limiting both the high-side MOSFET and low-side MOSFET. In an extended overcurrent condition, the device enters hiccup mode. Different protections are active during positive inductor current and negative inductor current conditions. Positive Inductor Current Protection Current is sensed in the high-side MOSFET while it is conducting after a short blanking time to allow noise to settle. Whenever the high-side overcurrent threshold is exceeded, the high-side MOSFET is immediately turned off and the low-side MOSFET is turned on. The high-side MOSFET does not turn back on until the current falls below the low-side MOSFET overcurrent threshold, effectively limiting the peak current in the case of a short-circuit condition. If a high-side overcurrent is detected for 15 consecutive cycles, the device enters hiccup mode. The current is also sensed in the low-side MOSFET while it is conducting after a short blanking time to allow noise to settle. If the low-side overcurrent threshold is exceeded when the next incoming PWM signal is received from the controller, the device skips processing that PWM pulse. The device does not turn the high-side MOSFET on again until the low-side overcurrent threshold is no longer exceeded. If the low-side overcurrent threshold remains exceeded for 15 consecutive cycles, the device enters hiccup. There are two separate counters for the high-side and low-side overcurrent events. If the off time is too short, the low-side overcurrent can not trip. The low-side overcurrent, however, begins tripping after the high-side peak overcurrent limit is crossed, as exceeding the peak current limit shortens the on time and lengthens the off time. Both the high-side and low-side positive overcurrent thresholds are programmable using the MSEL pin. Two sets of thresholds are available ("High" and "Low"), which are summarized in #GUID-DA4E932E-0802-40B1-A788-EA15C2F7A418/TB001005. The values for these thresholds are obtained using open-loop measurements with a DC current to accurately specify the values. In real applications, the inductor current ramps and the ramp rate is a function of the voltage across the inductor (VIN – VOUT) as well as the inductance value. The ramp rate combined with delays in the current sense circuitry then results in slightly different values than specified. The current at which the high-side overcurrent limit takes effect can be slightly higher than specified, and the current at which the low-side overcurrent limit takes effect can be slightly lower than specified. Overcurrent Thresholds MSEL Current Limit Setting High-Side Overcurrent Typical Value (A) Low-Side Overcurrent Typical Value (A) High 29 22 Low 23 17.6 Negative Inductor Current Protection Negative current is sensed in the low-side MOSFET while it is conducting after a short blanking time to allow noise to settle. Whenever the low-side negative overcurrent threshold is exceeded, the low-side MOSFET is immediately turned off. The next high-side MOSFET turn-on is determined by the clock and PWM comparator. The negative overcurrent threshold minimum value is 7 A. Similar to the positive inductor current protections, the actual value of the inductor current when the current sense comparators trip is a function of the current ramp rate. As a result, the current at which the negative inductor current limit takes effect can be slightly more negative than specified. Output Overvoltage and Undervoltage Protection The TPSM843B22 incorporates both output overvoltage and undervoltage protection. If an overvoltage is detected, the device tries to discharge the output voltage to a safe level before attempting to restart. When the overvoltage threshold is exceeded, the low-side MOSFET is turned on until the low-side negative overcurrent threshold is reached. At this point, the high-side MOSFET is turned on until the inductor current reaches zero. Then, the low-side MOSFET is turned back on until the low-side negative overcurrent threshold is reached. The process repeats until the output voltage falls back into the PG window. After this happens, the device restarts and goes through a soft start cycle. The device does not wait the hiccup time before restarting. When an undervoltage condition is detected, the device enters hiccup where it waits seven soft-start cycles before restarting. Undervoltage protection is enabled after soft start is complete. Overtemperature Protection When the die temperature exceeds 165°C, the device turns off. After the die temperature cools below the hysteresis level, typically by 12°C, the device restarts. While waiting for the temperature to fall below the hysteresis level, the device does not switch or attempt to hiccup to restart. After the temperature falls below the hysteresis level, the device restarts without going through hiccup. Output Voltage Discharge When the TPSM843B22 is enabled, but the high-side FET and low-side FET are disabled due to a fault condition, the output voltage discharge mode is enabled, turning on the discharge FET from SW to PGND to discharge the output voltage. The discharge FET is turned off when the converter is ready to resume switching, either after the fault clears or after the wait time before hiccup is over. The output voltage discharge mode is activated by any of the following fault events: High-side or low-side positive overcurrent Thermal shutdown Output voltage undervoltage VIN UVLO Device Functional Modes Forced Continuous-Conduction Mode The TPSM843B22 operates in forced continuous-conduction mode (FCCM) throughout normal operation. Discontinuous Conduction Mode During Soft Start At the beginning of soft start, the converter operates in discontinuous conduction mode (DCM) for the first 16 PWM cycles. During this time, a zero-cross detect comparator is used to turn off the low-side MOSFET when the current reaches zero amps, preventing the discharge of any prebiased conditions on the output. After the 16 cycles of DCM, the converter enters FCCM mode for the remainder of start-up and into regulation. Detailed Description Overview The TPSM843B22 is a 20-A, high-performance, synchronous buck module with two integrated N-channel MOSFETs, inductor, and several passives. The TPSM843B22 has a maximum operating junction temperature of 125°C, making it designed for high-ambient temperature applications such as wireless infrastructure, wired optical modules and test and measurement applications. The input voltage range is 4 V to 18 V and the output voltage range is 0.5 V to 7 V. The module features a fixed-frequency advanced current mode (ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter components. The switching frequency of the device can be synchronized to an external clock applied to the FSEL/SYNC pin. Advanced current mode is an emulated peak current-mode control topology, supporting stable static and transient operation without the requirement for a complex external compensation design. ACM includes an internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-noise ratio for good noise immunity. The TPSM843B22 has three ramp options to optimize the internal feedback loop for various inductor and output capacitor combinations with only a single resistor to AGND (see for details). The TPSM843B22 is easy to use and allows low external component count with fast load transient response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise. Overview The TPSM843B22 is a 20-A, high-performance, synchronous buck module with two integrated N-channel MOSFETs, inductor, and several passives. The TPSM843B22 has a maximum operating junction temperature of 125°C, making it designed for high-ambient temperature applications such as wireless infrastructure, wired optical modules and test and measurement applications. The input voltage range is 4 V to 18 V and the output voltage range is 0.5 V to 7 V. The module features a fixed-frequency advanced current mode (ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter components. The switching frequency of the device can be synchronized to an external clock applied to the FSEL/SYNC pin. Advanced current mode is an emulated peak current-mode control topology, supporting stable static and transient operation without the requirement for a complex external compensation design. ACM includes an internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-noise ratio for good noise immunity. The TPSM843B22 has three ramp options to optimize the internal feedback loop for various inductor and output capacitor combinations with only a single resistor to AGND (see for details). The TPSM843B22 is easy to use and allows low external component count with fast load transient response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise. The TPSM843B22 is a 20-A, high-performance, synchronous buck module with two integrated N-channel MOSFETs, inductor, and several passives. The TPSM843B22 has a maximum operating junction temperature of 125°C, making it designed for high-ambient temperature applications such as wireless infrastructure, wired optical modules and test and measurement applications. The input voltage range is 4 V to 18 V and the output voltage range is 0.5 V to 7 V. The module features a fixed-frequency advanced current mode (ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter components. The switching frequency of the device can be synchronized to an external clock applied to the FSEL/SYNC pin. Advanced current mode is an emulated peak current-mode control topology, supporting stable static and transient operation without the requirement for a complex external compensation design. ACM includes an internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-noise ratio for good noise immunity. The TPSM843B22 has three ramp options to optimize the internal feedback loop for various inductor and output capacitor combinations with only a single resistor to AGND (see for details). The TPSM843B22 is easy to use and allows low external component count with fast load transient response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise. The TPSM843B22 is a 20-A, high-performance, synchronous buck module with two integrated N-channel MOSFETs, inductor, and several passives. The TPSM843B22 has a maximum operating junction temperature of 125°C, making it designed for high-ambient temperature applications such as wireless infrastructure, wired optical modules and test and measurement applications. The input voltage range is 4 V to 18 V and the output voltage range is 0.5 V to 7 V. The module features a fixed-frequency advanced current mode (ACM) control architecture with five switching frequency selection settings ranging from 500 kHz to 2.2 MHz, allowing for efficiency and size optimization when selecting output filter components. The switching frequency of the device can be synchronized to an external clock applied to the FSEL/SYNC pin.TPSM843B2220TPSM843B22Advanced current mode is an emulated peak current-mode control topology, supporting stable static and transient operation without the requirement for a complex external compensation design. ACM includes an internal ramp generation network that emulates inductor current information, enabling the use of low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal-to-noise ratio for good noise immunity. The TPSM843B22 has three ramp options to optimize the internal feedback loop for various inductor and output capacitor combinations with only a single resistor to AGND (see for details). The TPSM843B22 is easy to use and allows low external component count with fast load transient response. Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise.TPSM843B22 TPSM843B22 Functional Block Diagram Functional Block Diagram Feature Description VIN Pins and VIN UVLO The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV. A second means to enable the device is provided by interfacing to the EN pin. See for more details. Internal Bypassing (BP5) The BP5 pin is the bypass pin for internal analog circuitry. This pin is connected internally to the VCC and VDRV pins of the converter with internal bypass capacitors of 0.1 μF to VCC and 2.2 μF to VDRV pins of the internal converter. This pin is bypassed internally and no external bypassing is required. Enable and Adjustable UVLO The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin. Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in . The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using and . When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage. Adjustable UVLO Using EN Internal Sequence of Events During Start-up The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. Internal Start-up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). Switching Frequency Selection The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in #GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001. Use a 1% tolerance resistor or better. Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 Switching Frequency Synchronization to an External Clock The TPSM843B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See . Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. Internal PWM Oscillator Frequency When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 Loss of Synchronization If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition Interfacing the SYNC/FSEL Pin If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA. Interfacing the SYNC/FSEL Pin with a Buffer Remote Sense Amplifier and Adjusting the Output Voltage Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load. The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as shown in . Use 1% tolerance or better divider resistors. FB Resistor Divider Starting with a fixed value for the bottom resistor, typically 10 kΩ, use to calculate the top resistor in the divider. Loop Compensation Guidelines The TPSM843B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections. Output Filter Inductor Tradeoffs The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. Ramp Capacitor Selection The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in . Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application. First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings Output Capacitor Selection Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Design Method for Good Transient Response The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. Soft Start and Prebiased Output Start-up During start-up, the device softly increases the reference voltage from zero to its final value, thereby reducing converter inrush current. There are four options for the soft-start time, which is the time it takes for the reference to ramp to 0.5 V: 1 ms 2 ms 4 ms 8 ms The soft-start time is selected with a resistor to AGND on the MSEL pin. See . If a prebiased output condition exists prior to start-up, the device prevents current from being discharged from the output. During monotonic prebiased start-up, the low-side MOSFET is not allowed to sink current until the SS pin voltage is higher than the FB pin voltage and the high-side MOSFET begins to switch. The one exception is if the BOOT-SW voltage is below its UVLO threshold. While in BOOT-SW UVLO, the low-side MOSFET is allowed to turn on to charge the BOOT capacitor. The low-side MOSFET reverse current protection provides another layer of protection for the device after the high-side MOSFET begins to switch. MSEL Pin The ramp amplitude, soft-start time, and current limit settings are programmed with a single resistor, RMSEL, from MSEL to AGND. #GUID-AE26DD20-5F78-4B29-B9E7-9BEBDB0372D3/TB001004 lists the resistor values for the available options. Use a 1% tolerance resistor or better. See for the corresponding current limit thresholds for the "High" and "Low" settings. MSEL Pin Selection RMSEL (kΩ) Current Limits CRAMP (pF) Soft-Start Time (ms) 1.78 High 1 1 2.21 High 1 2 2.74 High 1 4 3.32 High 1 8 4.02 High 2 1 4.87 High 2 2 5.9 High 2 4 7.32 High 2 8 9.09 High 4 1 11.3 High 4 2 14.3 High 4 4 18.2 High 4 8 22.1 Low 1 1 26.7 Low 1 2 33.2 Low 1 4 40.2 Low 1 8 49.9 Low 2 1 60.4 Low 2 2 76.8 Low 2 4 102 Low 2 8 137 Low 4 1 174 Low 4 2 243 Low 4 4 412 Low 4 8 Power Good (PG) The TPSM843B22 PG pin is an open-drain output requiring an external pullup resistor to output a high signal. After the FB pin is between 92% and 108% of the internal voltage reference, soft start is complete, and after a 256-µs deglitch time, the PG pin is de-asserted and the pin floats. TI recommends a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. PG is in a defined state after the VIN input voltage is greater than 1 V but with reduced current sinking capability. When the FB is lower than 84% or greater than 116% of the nominal internal reference voltage, after a 8-µs deglitch time, the PG pin is pulled low. PG is immediately pulled low if VIN falls below its UVLO, the EN pin is pulled low or the device enters thermal shutdown. Output Overload Protection The TPSM843B22 protects against output overload (that is, overcurrent) events by cycle-by-cycle current limiting both the high-side MOSFET and low-side MOSFET. In an extended overcurrent condition, the device enters hiccup mode. Different protections are active during positive inductor current and negative inductor current conditions. Positive Inductor Current Protection Current is sensed in the high-side MOSFET while it is conducting after a short blanking time to allow noise to settle. Whenever the high-side overcurrent threshold is exceeded, the high-side MOSFET is immediately turned off and the low-side MOSFET is turned on. The high-side MOSFET does not turn back on until the current falls below the low-side MOSFET overcurrent threshold, effectively limiting the peak current in the case of a short-circuit condition. If a high-side overcurrent is detected for 15 consecutive cycles, the device enters hiccup mode. The current is also sensed in the low-side MOSFET while it is conducting after a short blanking time to allow noise to settle. If the low-side overcurrent threshold is exceeded when the next incoming PWM signal is received from the controller, the device skips processing that PWM pulse. The device does not turn the high-side MOSFET on again until the low-side overcurrent threshold is no longer exceeded. If the low-side overcurrent threshold remains exceeded for 15 consecutive cycles, the device enters hiccup. There are two separate counters for the high-side and low-side overcurrent events. If the off time is too short, the low-side overcurrent can not trip. The low-side overcurrent, however, begins tripping after the high-side peak overcurrent limit is crossed, as exceeding the peak current limit shortens the on time and lengthens the off time. Both the high-side and low-side positive overcurrent thresholds are programmable using the MSEL pin. Two sets of thresholds are available ("High" and "Low"), which are summarized in #GUID-DA4E932E-0802-40B1-A788-EA15C2F7A418/TB001005. The values for these thresholds are obtained using open-loop measurements with a DC current to accurately specify the values. In real applications, the inductor current ramps and the ramp rate is a function of the voltage across the inductor (VIN – VOUT) as well as the inductance value. The ramp rate combined with delays in the current sense circuitry then results in slightly different values than specified. The current at which the high-side overcurrent limit takes effect can be slightly higher than specified, and the current at which the low-side overcurrent limit takes effect can be slightly lower than specified. Overcurrent Thresholds MSEL Current Limit Setting High-Side Overcurrent Typical Value (A) Low-Side Overcurrent Typical Value (A) High 29 22 Low 23 17.6 Negative Inductor Current Protection Negative current is sensed in the low-side MOSFET while it is conducting after a short blanking time to allow noise to settle. Whenever the low-side negative overcurrent threshold is exceeded, the low-side MOSFET is immediately turned off. The next high-side MOSFET turn-on is determined by the clock and PWM comparator. The negative overcurrent threshold minimum value is 7 A. Similar to the positive inductor current protections, the actual value of the inductor current when the current sense comparators trip is a function of the current ramp rate. As a result, the current at which the negative inductor current limit takes effect can be slightly more negative than specified. Output Overvoltage and Undervoltage Protection The TPSM843B22 incorporates both output overvoltage and undervoltage protection. If an overvoltage is detected, the device tries to discharge the output voltage to a safe level before attempting to restart. When the overvoltage threshold is exceeded, the low-side MOSFET is turned on until the low-side negative overcurrent threshold is reached. At this point, the high-side MOSFET is turned on until the inductor current reaches zero. Then, the low-side MOSFET is turned back on until the low-side negative overcurrent threshold is reached. The process repeats until the output voltage falls back into the PG window. After this happens, the device restarts and goes through a soft start cycle. The device does not wait the hiccup time before restarting. When an undervoltage condition is detected, the device enters hiccup where it waits seven soft-start cycles before restarting. Undervoltage protection is enabled after soft start is complete. Overtemperature Protection When the die temperature exceeds 165°C, the device turns off. After the die temperature cools below the hysteresis level, typically by 12°C, the device restarts. While waiting for the temperature to fall below the hysteresis level, the device does not switch or attempt to hiccup to restart. After the temperature falls below the hysteresis level, the device restarts without going through hiccup. Output Voltage Discharge When the TPSM843B22 is enabled, but the high-side FET and low-side FET are disabled due to a fault condition, the output voltage discharge mode is enabled, turning on the discharge FET from SW to PGND to discharge the output voltage. The discharge FET is turned off when the converter is ready to resume switching, either after the fault clears or after the wait time before hiccup is over. The output voltage discharge mode is activated by any of the following fault events: High-side or low-side positive overcurrent Thermal shutdown Output voltage undervoltage VIN UVLO Feature Description VIN Pins and VIN UVLO The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV. A second means to enable the device is provided by interfacing to the EN pin. See for more details. VIN Pins and VIN UVLO The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV. A second means to enable the device is provided by interfacing to the EN pin. See for more details. The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV. A second means to enable the device is provided by interfacing to the EN pin. See for more details. The VIN pin voltage supplies the internal control circuits of the device and provides the input voltage to the power stage. The input voltage for VIN can range from 4 V to 18 V. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold for start-up is 3.95 V typically with hysteresis of 150 mV.INININA second means to enable the device is provided by interfacing to the EN pin. See for more details. Internal Bypassing (BP5) The BP5 pin is the bypass pin for internal analog circuitry. This pin is connected internally to the VCC and VDRV pins of the converter with internal bypass capacitors of 0.1 μF to VCC and 2.2 μF to VDRV pins of the internal converter. This pin is bypassed internally and no external bypassing is required. Internal Bypassing (BP5) The BP5 pin is the bypass pin for internal analog circuitry. This pin is connected internally to the VCC and VDRV pins of the converter with internal bypass capacitors of 0.1 μF to VCC and 2.2 μF to VDRV pins of the internal converter. This pin is bypassed internally and no external bypassing is required. The BP5 pin is the bypass pin for internal analog circuitry. This pin is connected internally to the VCC and VDRV pins of the converter with internal bypass capacitors of 0.1 μF to VCC and 2.2 μF to VDRV pins of the internal converter. This pin is bypassed internally and no external bypassing is required. The BP5 pin is the bypass pin for internal analog circuitry. This pin is connected internally to the VCC and VDRV pins of the converter with internal bypass capacitors of 0.1 μF to VCC and 2.2 μF to VDRV pins of the internal converter. This pin is bypassed internally and no external bypassing is required. Enable and Adjustable UVLO The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin. Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in . The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using and . When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage. Adjustable UVLO Using EN Internal Sequence of Events During Start-up The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. Internal Start-up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). Enable and Adjustable UVLO The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin. Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in . The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using and . When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage. Adjustable UVLO Using EN The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin. Alternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in . The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using and . When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage. Adjustable UVLO Using EN The EN pin provides means for on and off control of the device. After the EN pin voltage exceeds its threshold voltage, the device begins a start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, IP, allowing the pin to be floated to enable the device by default. Ensure that leakage current of any circuitry connected to the EN pin does not exceed the minimum EN pullup current, otherwise the device can not be able to start. If an application requires digital control of the ENABLE function, an open-drain or open-collector output logic can be interfaced with the pin.PAlternatively, an external resistor divider can be added from VIN to the EN pin for adjustable UVLO as shown in . The EN pin pullup hysteresis current, Ih, is used to control the voltage hysteresis for the UVLO function by increasing the pin sourcing current after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using and . When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any noise on the input voltage.Ih Adjustable UVLO Using EN Adjustable UVLO Using EN Internal Sequence of Events During Start-up The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. Internal Start-up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). Internal Sequence of Events During Start-up The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. Internal Start-up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state. The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins. Internal Start-up Sequence If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). The enable feature of the TPSM843B22 provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843B22 reads the pin strap configuration as determined by the MSEL pin (see ) and SYNC/FSEL pin (see ) settings, and then enters a standby state.TPSM843B22TPSM843B22The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843B22 initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins.TPSM843B22 Internal Start-up Sequence Internal Start-up SequenceIf the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical). Switching Frequency Selection The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in #GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001. Use a 1% tolerance resistor or better. Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 Switching Frequency Selection The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in #GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001. Use a 1% tolerance resistor or better. Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in #GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001. Use a 1% tolerance resistor or better. Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 The switching frequency of the device is selected by connecting a resistor (RFSEL) from the SYNC/FSEL pin to AGND. The frequency options and their corresponding programming resistors are listed in #GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001. Use a 1% tolerance resistor or better.FSEL#GUID-236A7D73-F22C-438E-97EA-887603A7EE6C/TB001001 Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 Switching Frequency Selection RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) RFSEL Allowed Nominal Range (1%) (kΩ) Recommended E96 Standard Value (1%) (kΩ) Recommended E12 Standard Value (1%) (kΩ) fSW (kHz) RFSEL Allowed Nominal Range (1%) (kΩ)FSELRecommended E96 Standard Value (1%) (kΩ)Recommended E12 Standard Value (1%) (kΩ)fSW (kHz)SW ≥ 24.0 24.3 27.0 500 17.4 – 18.0 17.4 17.8 750 11.8 – 12.1 11.8 12.1 1000 8.06 – 8.25 8.06 8.25 1500 ≤ 5.11 4.99 4.75 2200 ≥ 24.0 24.3 27.0 500 ≥ 24.024.327.0500 17.4 – 18.0 17.4 17.8 750 17.4 – 18.017.417.8750 11.8 – 12.1 11.8 12.1 1000 11.8 – 12.111.812.11000 8.06 – 8.25 8.06 8.25 1500 8.06 – 8.258.068.251500 ≤ 5.11 4.99 4.75 2200 ≤ 5.114.994.752200 Switching Frequency Synchronization to an External Clock The TPSM843B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See . Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. Internal PWM Oscillator Frequency When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 Loss of Synchronization If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition Interfacing the SYNC/FSEL Pin If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA. Interfacing the SYNC/FSEL Pin with a Buffer Switching Frequency Synchronization to an External Clock The TPSM843B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See . Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. The TPSM843B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See . Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. The TPSM843B22 can be synchronized to an external clock by applying a square wave clock signal to the SYNC/FSEL pin with a duty cycle from 20% to 80%. The external clock can either be applied before the device starts up or during operation. If the external clock is applied before the device starts, a resistor from SYNC/FSEL to AGND is not needed. If the external clock is applied after the device starts, then the clock frequency must be within ±20% of the frequency set by the SYNC/FSEL resistor. When the external clock is applied after the device starts, the device begins synchronizing to this external clock after counting four consecutive switching cycles with the external clock pulse present. See .TPSM843B22Although there is no internal circuit to detect the higher 20% range of the clock frequency, it falls outside the stability range of the LC design so it is imposed as a requirement on the customer to ensure the synchronization clock is within ±20% of the frequency set by the SYNC/FSEL resistor. Internal PWM Oscillator Frequency When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 Internal PWM Oscillator Frequency When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency. If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present. If the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency. Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies. Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 When the external clock is present, the device synchronizes the switching frequency to the clock. Any time the external clock is not present, the device defaults to the internal PWM oscillator frequency.If the device starts up before an external clock signal is applied, then the internal PWM oscillator frequency is set by the RFSEL resistor according to . The device switches at this frequency until the external clock is applied or anytime the external clock is not present.FSELIf the external clock is applied before the device starts up, then the RFSEL resistor is not needed. The device then decodes the external clock frequency and selects an internal PWM oscillator frequency.FSEL Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 Internal Oscillator Frequency Decode External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) External Sync Clock Frequency (kHz) Decoded Internal PWM Oscillator Frequency (kHz) External Sync Clock Frequency (kHz)Decoded Internal PWM Oscillator Frequency (kHz) 400 – 600 500 600 – 857 750 857 – 1200 1000 1200 – 1810 1500 1810 – 2640 2200 400 – 600 500 400 – 600500 600 – 857 750 600 – 857750 857 – 1200 1000 857 – 12001000 1200 – 1810 1500 1200 – 18101500 1810 – 2640 2200 1810 – 26402200The thresholds for the external SYNC clock frequency ranges have approximately a ±5% tolerance. If the external clock frequency is within that tolerance range, it is possible for the internal PWM oscillator frequency to be decoded as either the frequency above or below that threshold. Because the internal frequency is what is used in case of the loss of the synchronization clock, TI recommends that the output LC filter and ramp selection are chosen for stability for either frequency. #GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 shows the tolerance range of the decode thresholds. If the external clock is to be within any of these ranges, TI recommends to design the converter to ensure converter stability for both possible internal PWM oscillator frequencies.#GUID-44F2C909-0A46-450F-B1F8-7A34232E52D1/TB001003 Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 Frequency Decode Thresholds Minimum (kHz) Typical (kHz) Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 Minimum (kHz) Typical (kHz) Maximum (kHz) Minimum (kHz) Typical (kHz) Maximum (kHz) Minimum (kHz)Typical (kHz)Maximum (kHz) 570 600 630 814 857 900 1140 1200 1260 1736 1810 1884 570 600 630 570600630 814 857 900 814857900 1140 1200 1260 114012001260 1736 1810 1884 173618101884 Loss of Synchronization If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition Loss of Synchronization If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition If at any time during operation, there is a loss of synchronization, the device defaults to the internal PWM oscillator frequency until the synchronization clock returns. After the clock is no longer present, the device switches at 70% of the internal clock frequency for four consecutive cycles. After four consecutive cycles without clock pulses, the device operates at the normal internal PWM oscillator frequency. Clock Synchronization Transition Clock Synchronization Transition Interfacing the SYNC/FSEL Pin If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA. Interfacing the SYNC/FSEL Pin with a Buffer Interfacing the SYNC/FSEL Pin If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA. Interfacing the SYNC/FSEL Pin with a Buffer If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA. Interfacing the SYNC/FSEL Pin with a Buffer If an application requires synchronizing to a SYNC clock but the clock is unavailable before the device is enabled, TI recommends a high impedance buffer to ensure proper detection of the RFSEL value. shows the recommended implementation. The leakage current into the buffer output must be less than 5 µA to ensure proper detection of the RFSEL value. Power the buffer from the BP5 output of the device to ensure its VCC voltage is available and the buffer output is high impedance before the device tries to detect the RFSEL value. When powering the buffer from the BP5 pin, the external load on the BP5 pin must be less than 2 mA.FSELFSELFSEL Interfacing the SYNC/FSEL Pin with a Buffer Interfacing the SYNC/FSEL Pin with a Buffer Remote Sense Amplifier and Adjusting the Output Voltage Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load. The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as shown in . Use 1% tolerance or better divider resistors. FB Resistor Divider Starting with a fixed value for the bottom resistor, typically 10 kΩ, use to calculate the top resistor in the divider. Remote Sense Amplifier and Adjusting the Output Voltage Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load. The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as shown in . Use 1% tolerance or better divider resistors. FB Resistor Divider Starting with a fixed value for the bottom resistor, typically 10 kΩ, use to calculate the top resistor in the divider. Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load. The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as shown in . Use 1% tolerance or better divider resistors. FB Resistor Divider Starting with a fixed value for the bottom resistor, typically 10 kΩ, use to calculate the top resistor in the divider. Remote sensing of the output voltage is provided through a dedicated high speed, low offset instrumentation type amplifier. Connect the output voltage setting resistive divider described below from the output voltage sensing point to the GOSNS pin. The center point is to be connected to the FB pin. Note the GOSNS pin is to be tied to the converter output voltage return at a location near to the load.The output voltage is programmed with a resistor divider from the converter output (VOUT) to the FB pin as shown in . Use 1% tolerance or better divider resistors.OUT FB Resistor Divider FB Resistor DividerStarting with a fixed value for the bottom resistor, typically 10 kΩ, use to calculate the top resistor in the divider. Loop Compensation Guidelines The TPSM843B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections. Output Filter Inductor Tradeoffs The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. Ramp Capacitor Selection The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in . Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application. First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings Output Capacitor Selection Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Design Method for Good Transient Response The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. Loop Compensation Guidelines The TPSM843B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections. The TPSM843B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections. The TPSM843B22 employs advanced current mode control (ACM) architecture to provide internal feedback loop compensation for most applications. By applying VIN, duty cycle, and low-side FET current information to generate an internal ramp combined with contribution from internally sensed inductor valley current, ACM cancels one of the poles of the output LC filter and provides phase compensation to ensure loop stability. As with any internal compensation scheme, certain design guidelines must be followed. Guidelines for a converter design are provided in the following sections.TPSM843B22IN Output Filter Inductor Tradeoffs The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. Output Filter Inductor Tradeoffs The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. The selection of the output inductor is one of the most important choices to make in designing the module. The following is a short list of considerations which were done when determining the value of the inductor used in this module. Start with an inductor value that results in a ripple current (ΔI) between 30% and 50% of full load. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L= V I N - V O U T ∆ I V I N - V O U T V I N - V O U T V I N - V O U T V I N V V I N IN - V O U T V V O U T OUT ∆ I ∆I× V O U T V I N V O U T V O U T V V O U T OUT V I N V I N V V I N IN× 1 f S W 1 1 f S W f S W f f S W SW A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response. The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold. The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. A choice of inductor value has a direct correlation to load transient response. Too large an inductor value can result in poor load transient response.The ripple current has an impact on the DC load current at which the converter enters current limit. Ensure that the peak valley current at full load is less than the current limit threshold by an adequate margin. A recommended range is 60% to 80% of the current limit threshold.The ripple current has an impact on the RMS losses of the converter. The higher the ripple current, the higher the RMS losses. Ramp Capacitor Selection The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in . Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application. First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings Ramp Capacitor Selection The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in . Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application. First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in . Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application. First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings The TPSM843B22 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see ). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in .TPSM843B22RAMPRAMPMany applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application.RAMPRAMP First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P First, calculate the RAMP time constant using and . τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N τ C R A M P = C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N τ C R A M P τ τ C R A M P CRAMP= C R A M P × 10 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N C R A M P × 10 6 C R A M P C C R A M P RAMP × 10 6 10 10 6 6 L o o k u p 1 - L o o k u p 2 × V O U T V I N Lookup1 - Lookup2 × V O U T V I N V O U T V O U T V V O U T OUT V I N V I N V V I N IN RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 RAMP Selection Lookup Values fSW (kHz) Lookup1 Value Lookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 fSW (kHz) Lookup1 Value Lookup2 Value fSW (kHz) Lookup1 Value Lookup2 Value fSW (kHz)SWLookup1 ValueLookup2 Value 500 0.372 0.297 750 0.548 0.445 1000 0.719 0.594 1500 1.04 0.891 2200 1.46 1.31 500 0.372 0.297 5000.3720.297 750 0.548 0.445 7500.5480.445 1000 0.719 0.594 10000.7190.594 1500 1.04 0.891 15001.040.891 2200 1.46 1.31 22001.461.31Next, calculate the RAMP capacitor voltage to ensure the capacitor chosen for CRAMP does not result in a ramp amplitude of greater than 1.25 V, which ensures the ramp does not saturate to ground during a load transient. V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P RAMP V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P V C R A M P = V I N × ( t O N + 100 ns ) τ C R A M P V C R A M P V V C R A M P CRAMP= V I N × ( t O N + 100 ns ) τ C R A M P V I N × ( t O N + 100 ns ) V I N V V I N IN × ( t O N ( t (t O N ON + 100 ns) τ C R A M P τ C R A M P τ τ C R A M P CRAMP A larger CRAMP capacitance results in highest loop gain. A smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency. A larger CRAMP capacitance results in highest loop gain.RAMPA smaller CRAMP capacitance requires fewer output capacitors, and results in a higher crossover frequency.RAMP and show how the loop changes with each ramp setting for the schematic in . Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings Loop Gain vs Ramp Settings Loop Gain vs Ramp Settings Loop Phase vs Ramp Settings Loop Phase vs Ramp Settings Output Capacitor Selection Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Output Capacitor Selection Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability. The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease. The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C Ensure the ESR zero frequency of the capacitors used is at least 5 × the expected crossover frequency. This way, the impact of the ESR on the loop gain is reduced to a manageable level. f E S R _ Z E R O = 1 2 π × R E S R × C f E S R _ Z E R O = 1 2 π × R E S R × C f E S R _ Z E R O = 1 2 π × R E S R × C f E S R _ Z E R O = 1 2 π × R E S R × C f E S R _ Z E R O f f E S R _ Z E R O ESR_ZERO= 1 2 π × R E S R × C 1 1 2 π × R E S R × C 2π × R E S R R R E S R ESR × C The amount of output capacitance has a direct impact on the closed loop bandwidth of the converter. Too little capacitance and the bandwidth can be too high to maintain stability.The amount of output capacitance has a direct impact on output voltage overshoot during a load drop. Too little capacitance and the stored energy in the output inductor can cause the output voltage to overshoot during a sharp load decrease.The impedance of the output capacitance (impedance of the capacitors plus ESR) has an impact on the output ripple noise of the converter. Too high an impedance (due to not enough capacitance, too high ESR, or both) can result in output ripple above system requirements. V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C V R I P P L E = ∆ I × R E S R + 1 2 π × f S W × C V R I P P L E V V R I P P L E RIPPLE=∆I× R E S R + 1 2 π × f S W × C R E S R + 1 2 π × f S W × C R E S R R R E S R ESR+ 1 2 π × f S W × C 1 1 2 π × f S W × C 2π × f S W f f S W SW × C Design Method for Good Transient Response The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. Design Method for Good Transient Response The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. The following method to design converter compensation optimizes the load transient response. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Select a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W Calculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Calculate the minimum output capacitance required to meet the impedance requirements. C O U T _ M I N = 1 2 π × Z O U T _ C O N V E R T E R × f C O _ D E S I R E D where fCO_DESIRED is the desired converter closed loop crossover frequency, which is usually 1/8 to 1/4 of the converter switching frequency. Calculate the number of output capacitors required. From the previous section, use the guidelines for ESR to select a capacitor type and value, then use the equation here to find the number of capacitors required. Notice that the impedance of the capacitors (ESR plus impedance of the capacitance itself at the chosen crossover frequency) is used. Z C A P A C I T O R = R E S R _ C A P A C I T O R + 1 2 π × C C A P A C I T O R × F C O N C A P A C I T O R S = Z C A P A C I T O R Z O U T _ C O N V E R T E R Using one of the tools on TI.com, simulate with the values for the design. Calculate the require output impedance to meet transient response goals. This equation assumes the load step transient is faster than the BW of the converter. Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Z O U T _ R E Q U I R E D = d e l t a _ V O U T d e l t a _ I O U T Z O U T _ R E Q U I R E D Z Z O U T _ R E Q U I R E D OUT_REQUIRED= d e l t a _ V O U T d e l t a _ I O U T d e l t a _ V O U T d e l t a _ V O U T d e l t a _ V delta_V O U T OUT d e l t a _ I O U T d e l t a _ I O U T d e l t a _ I delta_I O U T OUTSelect a value for output inductance. L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L = V I N - V O U T ∆ I × V O U T V I N × 1 f S W L= V I N - V O U T ∆ I V I N - V O U T V I N - V O U T V I N - V O U T V I N V V I N IN - V O U T V V O U T OUT ∆ I ∆I× V O U T V I N V O U T V O U T V V O U T OUT V I N V I N V V I N IN× 1 f S W 1 1 f S W f S W f f S W SWCalculate the required converter output impedance to meet the transient response goal. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Ensure ZOUT_CONVERTER is less than the ZOUT_REQUIRED found in step 1. Also recheck the voltage on CRAMP is within acceptable limits. (see previous section) If it is too large, use a larger CRAMP value. Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Z O U T _ C O N V E R T E R = 0.00135 + L τ C R A M P 34 × V O U T V R E F Z O U T _ C O N V E R T E R = 0.00135 + L τ