14-Bit, 62-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 62 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 300 Features High Performance Rating Catalog Input range (Vp-p) 2, 4 Power consumption (Typ) (mW) 1200 Architecture Pipeline SNR (dB) 73 ENOB (Bits) 11.7 SFDR (dB) 85 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

LQFP (PM) 64 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)


         High SFDR: 85dB at 10MHz fIN
         High SNR: 72dB at 10MHz fIN
         Differential Inputs
         Selectable Full-Scale Input Range
         Differential or Single-Ended
         Accepts Sine or Square Wave Clocking Down to 0.5VPP
         Variable Threshold Level

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open-in-new Find other High-speed ADCs (>10MSPS)


The ADS5422 is a high-dynamic range, 14-bit, 62MSPS, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold amplifier that gives good spurious performance up to the Nyquist rate. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5VPP, further improving the Signal-to-Noise Ratio (SNR) performance.

The ADS5422 has a 4VPP differential input range (2VPP • 2 inputs) for optimum Spurious-Free Dynamic Range (SFDR). The differential operation gives the lowest even-order harmonic components. A lower input voltage can also be selected using the internal references, further optimizing SFDR.

The ADS5422 is available in an LQFP-64 package.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

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No results found. Please clear your search and try again. View all 13
Type Title Date
* Datasheet 14-Bit, 62MSPS Sampling Analog-To-Digital Converter datasheet (Rev. D) Jun. 22, 2005
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Application notes Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application notes Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
Application notes High-Speed, Analog-to-Digital Converter Basics Jan. 11, 2012
Application notes Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application notes Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
User guides ADS5421/22EVM Jan. 30, 2003

Design & development

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Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Analog-to-digital converter (ADC) harmonic calculator

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

Jitter and SNR Calculator for ADCs
JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

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LQFP (PM) 64 View options

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