Home Microcontrollers (MCUs) & processors Arm-based processors
Home
Microcontrollers (MCUs) & processors
Arm-based processors
NEW

AM68

ACTIVE

General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0

Order now
Data sheet
User guides
Errata

AM68

ACTIVE
Data sheet Order now

Product details

Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 3 Hardware accelerators 1 video encode/decode accelerator Features General purpose, USB 3.0 Operating system Linux Security Cryptography, Debug security, Device Identity, Secure boot, Secure storage & programming Rating Automotive Operating temperature range (°C) -40 to 105
Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 3 Hardware accelerators 1 video encode/decode accelerator Features General purpose, USB 3.0 Operating system Linux Security Cryptography, Debug security, Device Identity, Secure boot, Secure storage & programming Rating Automotive Operating temperature range (°C) -40 to 105
FCBGA (ALZ) 770 529 mm² 23 x 23

Processor cores:

  • Up to dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex-A72 core
  • Deep Learning Accelerator:
    • Up to 8 Trillion Operations Per Second (TOPS)
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem supports:
    • Up to 4 displays
    • Up to two DSI 4L TX (up to 2.5K)
    • One eDP 4L
    • One DPI 24-bit RGB parallel interface
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Safety features such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64, up to 800 MHz
    • 50 GFLOPS, 4 GTexels/s
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
    • 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to two 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • Up to two 512KB on-chip SRAM in MAIN domain, protected by ECC

Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX
  • Two Ethernet RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface (eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

Technology / Package:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Processor cores:

  • Up to dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex-A72 core
  • Deep Learning Accelerator:
    • Up to 8 Trillion Operations Per Second (TOPS)
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem supports:
    • Up to 4 displays
    • Up to two DSI 4L TX (up to 2.5K)
    • One eDP 4L
    • One DPI 24-bit RGB parallel interface
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Safety features such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64, up to 800 MHz
    • 50 GFLOPS, 4 GTexels/s
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
    • 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to two 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • Up to two 512KB on-chip SRAM in MAIN domain, protected by ECC

Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX
  • Two Ethernet RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface (eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

Technology / Package:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within the lowest power envelope in the industry even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of processors.

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within the lowest power envelope in the industry even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of processors.

open-in-new Find other Arm-based processors
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 3
Type Title Date
* Data sheet AM68x Processors, Silicon Revision 1.0 datasheet (Rev. A) PDF | HTML 18 Aug 2023
* Errata J721S2, TDA4VE, TDA4AL, TDA4VL, AM68A Processor Silicon Errata (Rev. B) PDF | HTML 20 May 2023
* User guide J721S2, TDA4AL, TDA4VL, TDA4VE, AM68A Technical Reference Manual (Rev. C) PDF | HTML 26 Jun 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SK-AM68 — AM68x starter kit for Sitara™ processors

The SK-AM68 Starter Kit/Evaluation Module (EVM) is based on the AM68x vision SoC which includes an image signal processor (ISP) supporting up to 480MP/s, an 8 tera-operations-per-second (TOPS) AI accelerator, two 64-bit Arm® Cortex®-A72 CPUs, and support for H.264/H.265 video encode/decode. (...)

User guide: PDF | HTML
Not available on TI.com
Software development kit (SDK)

PROCESSOR-SDK-LINUX-AM68 — Processor SDK Linux for AM68

The AM68 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.


All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM68 — General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0
Hardware development
Evaluation board
SK-AM68 — AM68x starter kit for Sitara™ processors
Download options
IDE, configuration, compiler or debugger

C7000-CGT — C7000 code generation tools (CGT) - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
TDA4VM — Dual Arm® Cortex®-A72 SoC and C7x DSP with deep-learning, vision and multimedia accelerators TDA4VM-Q1 — Automotive system-on-a-chip for L2, L3 and near-field analytic systems using deep learning AM62A3 — 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power, video surveillance, retail automation AM62A7 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, low-power systems, machine vision, robotics AM62A3-Q1 — Automotive 1 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, dashcams AM62A7-Q1 — 2 TOPS vision SoC with RGB-IR ISP for 1-2 cameras, driver monitoring, front cameras AM69A — 32 TOPS vision SoC for 1-12 cameras, Autonomous Mobile Robots, Machine Vision, Mobile DVR, AI-BOX AM68 — General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0 AM68A — 8 TOPS vision SoC for 1-8 cameras, machine vision, smart traffic, retail automation
Download options
IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Products
Automotive mmWave radar sensors
AWR1243 — 76-GHz to 81-GHz high-performance automotive MMIC AWR1443 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating MCU and hardware accelerator AWR1642 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP and MCU AWR1843 — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR1843AOP — Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 — 76-GHz to 81-GHz automotive second-generation high-performance MMIC AWR2944 — Automotive 2nd-generation, 76-GHz to 81-GHz, high-performance SoC for corner and long-range radar AWR6443 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating DSP, MCU and radar accelerator AWR6843AOP — Single-chip 60-GHz to 64-GHz automotive radar sensor integrating antenna on package, DSP and MCU
Industrial mmWave radar sensors
IWR1443 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating MCU and hardware accelerator IWR1642 — Single-chip 76-GHz to 81-GHz mmWave sensor integrating DSP and MCU IWR1843 — Single-chip 76-GHz to 81-GHz industrial radar sensor integrating DSP, MCU and radar accelerator IWR6443 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating MCU and hardware accelerator IWR6843 — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor integrating processing capability IWR6843AOP — Single-chip 60-GHz to 64-GHz intelligent mmWave sensor with integrated antenna on package (AoP)
Launch Download options
Online training

AM68-ACADEMY — Designed to simplify and accelerate embedded development on AM68 processors

Customers new to TI’s powerful heterogeneous SoCs need training to get started, and then build advance applications using our SDK.
Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM68 — General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0
Hardware development
Evaluation board
SK-AM68 — AM68x starter kit for Sitara™ processors
Browse
Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Download
Package Pins Download
FCBGA (ALZ) 770 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos