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Product details

Parameters

Function Decoder, Demultiplexer Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Channels (#) 2 Voltage (Nom) (V) 10 F @ nom voltage (Max) (MHz) 8 ICC @ nom voltage (Max) (mA) 0.3 tpd @ nom Voltage (Max) (ns) 190 Configuration 1:4 Type Standard IOL (Max) (mA) 1.5 IOH (Max) (mA) -1.5 Rating Catalog Operating temperature range (C) -55 to 125 Bits (#) 4 Digital input leakage (Max) (uA) 5 ESD CDM (kV) 0.75 ESD HBM (kV) 2 open-in-new Find other Encoders & decoders

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Encoders & decoders

Features

  • Expandable with multiple packages
  • Standard, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range; 100 na at 18 V and 25°C
  • Noise margin (full package-temperature range):
         1 V at VDD = 5 V
         2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • Decoding
    • Code conversion
    • Demultiplexing (using Enable input as a data input)
    • Memory chip-enable selection
    • Function selection
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Description

CD4555B and CD4556B are dual one-of-four decoders/demultiplexers. Each decoder has two select inputs (A and B), an Enable input (E\), and four mutually exclusive outputs. On the CD4555B the outputs are high on select; on the CD4556B the outputs are low on select.

When the enable input is high, the outputs of the CD4555B remain low and the outputs of the CD4556B remain high regardless of the state of the select inputs A and B. The CD4555B and CD4556B are similar to types MC14555 and MC14556, respectively.

The CD4555B and CD4556B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastics packages (E suffix), and 16-lead small-outline packages (M, M96, and MT suffixes). The CD4555B is also supplied in 16-lead small-outline packages (NSR suffix) and 16-lead thin shrink small-outline packages (PW and PWR suffixes.)

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Technical documentation

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Type Title Date
* Datasheet CD4555B, CD4556B TYPES datasheet (Rev. D) Oct. 13, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options

Ordering & quality

Support & training

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Videos

Anatomy of a logic part number

Logic part numbers use a formulaic naming system to denote the device's functionality and features. This video reviews the components to a logic part's name.

Posted: 22-Jan-2018
Duration: 01:26

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