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Product details

Parameters

Technology Family AC Function Digital Multiplexer Configuration 4:1 Number of channels (#) 2 Supply voltage (Min) (V) 1.5 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type 3-State Data rate (Max) (Mbps) 200 ICC (Max) (uA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode open-in-new Find other Encoders & decoders

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Encoders & decoders

Features

  • Buffered Inputs
  • Typical Propagation Delay
    - 6.3ns at VCC = 5V, TA = 25°C, CL = 50pF
  • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • ±24mA Output Drive Current
    - Fanout to 15 FAST™ ICs
    - Drives 50 Transmission Lines
  • Characterized for operation from –40° to 85°C

FAST™ is a Trademark of Fairchild Semiconductor.

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Description

The CD74AC253 and ’ACT253 dual 4-input multiplexers that utilize Advanced CMOS Logic technology. One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Output Enable (1OE\ or 2OE\) is HIGH, the output is in the high-impedance state.

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Technical documentation

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Type Title Date
* Data sheet Dual 4-Input Multiplexer, Three-State datasheet (Rev. A) May 17, 2000
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature HiRel Unitrode Power Management Brochure Jul. 07, 2009
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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