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Product details

Parameters

Function Decoder, Demultiplexer Technology Family HCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 1 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 25 ICC @ nom voltage (Max) (mA) 0.08 tpd @ nom Voltage (Max) (ns) 44 Configuration 4:16 Type Standard IOL (Max) (mA) 4 IOH (Max) (mA) -4 Rating Catalog Operating temperature range (C) -55 to 125 Bits (#) 16 Digital input leakage (Max) (uA) 5 ESD CDM (kV) 0.75 ESD HBM (kV) 2 open-in-new Find other Encoders & decoders

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other Encoders & decoders

Features

  • Two Enable Inputs to Facilitate Demultiplexing and Cascading Functions
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL= 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

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Description

The ’HC154 and ’HCT154 are 4-to-16 line decoders/demultiplexers with two enable inputs, E1 and E2. A High on either enable input forces the output into the High state. The demultiplexing function is performed by using the four input lines, A0 to A3, to select the output lines Y0\ to Y15\, and using one enable as the data input while holding the other enable low.

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Technical documentation

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Type Title Date
* Datasheet CD54HC154, CD74HC154, CD54HCT154, CD74HCT154 datasheet (Rev. D) Jun. 22, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

Support & training

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Videos

Anatomy of a logic part number

Logic part numbers use a formulaic naming system to denote the device's functionality and features. This video reviews the components to a logic part's name.

Posted: 22-Jan-2018
Duration: 01:26

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