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Product details

Parameters

Technology Family FCT Function Digital Multiplexer Configuration 2:1 Number of channels (#) 4 Operating temperature range (C) -40 to 85 Rating Catalog open-in-new Find other Digital multiplexers & encoders

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 SOIC (DW) 16 77 mm² 7.52 x 10.28 SSOP (DBQ) 16 29 mm² 4.9 x 6 open-in-new Find other Digital multiplexers & encoders

Features

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • 3-State Outputs

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Description

The CY74FCT257T has four identical two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The I0 inputs are selected when S is low, and the I1 inputs are selected when S is high. Data at the output is noninverted.

The CY74FCT257T is a logic implementation of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. Outputs are in the high-impedance state when the output-enable (OE\) input is high.

All but one device must be in the high-impedance state to avoid currents exceeding the maximum ratings if outputs are tied together. OE\ inputs must ensure that there is no overlap when outputs of 3-state devices are tied together.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet Quad 2-Input Multiplexer With 3-State Outputs datasheet (Rev. D) Nov. 02, 2001
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guide CYFCT Parameter Measurement Information Apr. 02, 2001
Selection guide Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options
SOIC (DW) 16 View options
SSOP (DBQ) 16 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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